Quadrature Error Correction Circuit for 90-Degree Memory Clocks
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Solution Overview
Problem
Semiconductor memory devices face challenges in concurrently correcting clock signal skew and duty cycle errors, which affect the synchronization and performance of memory operations.
Innovation Solution
A quadrature error correction circuit is implemented, comprising a duty cycle adjusting circuit, phase splitters, a phase interpolator, and a delay control circuit, which adjusts the phase and delay of clock signals to concurrently correct skew and duty cycle errors, generating corrected clock signals with a 90-degree phase difference.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate correction circuits are used for skew and duty cycle errors, then each error can be corrected individually, but the device complexity increases and concurrent correction is not achieved
Solution Approach 1:
The patent combines skew correction and duty cycle correction functions into a single integrated quadrature error correction circuit. The duty cycle adjusting circuit and phase adjusting circuit work together within one unified structure, allowing concurrent correction of both types of errors without requiring separate independent circuits, thus reducing overall device complexity while maintaining high reliability
Solution Approach 2:
The quadrature error correction circuit is designed to perform multiple functions simultaneously: it corrects skew errors between clock signals, adjusts duty cycle errors of individual clock signals, and maintains the 90-degree phase relationship. This multi-functional approach eliminates the need for multiple specialized circuits and achieves comprehensive clock signal correction in a single device
2Measurement precision
If multiple separate adjustment stages are implemented for skew and duty cycle, then correction precision can be improved, but the adjustment complexity and time consumption increase
Solution Approach 1:
The correction circuit is segmented into distinct functional blocks: a duty cycle adjusting circuit that specifically handles duty cycle errors, and a phase adjusting circuit that handles skew errors. Each segment focuses on a specific correction task, allowing for precise adjustment of individual parameters without interfering with the other, thereby achieving high correction precision through modular functional division
Solution Approach 2:
The duty cycle adjusting circuit performs preliminary adjustment of the clock signal duty cycle before the phase adjusting circuit processes the skew correction. This sequential preliminary action ensures that each correction stage operates on already-optimized signals, improving overall precision while maintaining a clear and manageable adjustment flow
3Ease of manufacture
If conventional separate correction methods are used, then circuit design is simpler, but the correction time and loss of time increase
Solution Approach 1:
The quadrature error correction circuit operates continuously and concurrently on both skew and duty cycle errors without requiring sequential processing steps. The duty cycle adjusting circuit and phase adjusting circuit work in parallel, eliminating idle time between corrections and ensuring continuous optimization of clock signals, which significantly reduces the total correction time compared to conventional sequential methods
Data Source
AI summary
A quadrature error correction circuit includes a duty cycle adjusting circuit, a phase interpolator, a phase detector, and a delay control circuit. The duty cycle adjusting circuit generates a first corrected clock signal and a second corrected clock signal whose skew and duty cycle error are concurrently adjusted by adjusting a delay of edges of a second clock signal and adjusting a delay of a falling edge of a first clock signal based on first through fourth control code sets. The phase interpolator generates a second delayed and selected clock signal by delaying a second selected clock signal selected from first through fourth adjusted clock signals. A phase detector detects a phase difference between a first selected clock signal and the second delayed and selected clock signal to generate an up/down signal. The delay control circuit generates the first through fourth control code sets based on the up/down signal.