Memory Clock Duty Cycle Correction with Single-DLL Phase Mixing
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Solution Overview
Problem
Conventional digital duty cycle correction (DCC) technologies in semiconductor memories face challenges such as larger silicon area consumption, difficulty in phase matching of delay lock loops, and susceptibility to noise, while analogue DCC offers higher resolution but with larger static current and narrower correction range.
Innovation Solution
A duty cycle correction apparatus and method utilizing a delay line unit, output tap unit, and phase mixer to delay and mix clock signals, with a phase comparator and controller to achieve phase lock and reduce silicon area and power consumption, enabling rapid phase lock and correction.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If conventional digital DCC uses two delay lock loops for duty cycle correction, then the correction range is wide and static current is low, but the silicon area consumed is larger
Solution Approach 1:
The patent merges the functionality of two separate delay lock loops into a single unified DLL structure. The phase mixer combines clock signals from a single DLL to achieve duty cycle correction, eliminating the need for duplicate phase mixers, delay model units, and direct phase detectors. This consolidation maintains the wide correction range and low static current benefits of digital DCC while significantly reducing the silicon area required.
2Productivity
If conventional digital DCC uses two delay lock loops with multiple circuit elements, then the correction process is rapid, but the phase matching accuracy is difficult to achieve
Solution Approach 1:
The patent extracts and eliminates the redundant circuit elements (one set of phase mixer, delay model unit, and direct phase detector) from the conventional two-DLL architecture. By removing these duplicate components, the patent simplifies the phase matching process and improves accuracy while maintaining rapid correction speed through the streamlined single-DLL structure with integrated phase mixing functionality.
3Measurement precision
If analogue DCC is used for duty cycle correction, then the resolution is higher, but the static current is larger and correction range is narrower
Solution Approach 1:
The patent replaces the analogue DCC mechanism with a digital DCC approach using a single delay lock loop with phase mixing. This substitution maintains high correction resolution through precise digital phase control while significantly reducing static current consumption compared to analogue implementations. The digital phase mixer achieves fine resolution through digital signal processing rather than analogue voltage control.
Data Source
AI summary
The present invention is directed to a duty cycle correction apparatus that can be implemented in a small size, and is capable of performing a phase lock more rapidly, and reducing the amount of current being consumed, and to a method thereof. The duty cycle correction apparatus in accordance with the present invention for use in a semiconductor memory device includes a delay line unit for delaying a first clock signal to produce a first delayed clock signal; an output tap unit for delaying the first delayed clock signal by a pulse width of a first logic state of the first clock signal under the control of a toss control signal derived from a second clock signal; and a phase mixer for mixing the clock signal from the output tap unit and one of the first and second clock signals.