Semiconductor Memory Clock Phase Tracking for Accurate Data Sampling
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Solution Overview
Problem
In high-speed semiconductor memory systems, the delay in clock signal transmission paths can cause inaccuracies in data sampling due to variations in power supply voltage and temperature, leading to malfunctions, especially when the clock frequency exceeds 1 GHz, making it difficult to maintain data and clock signal synchronization within the effective window.
Innovation Solution
A data input/output apparatus and method that includes a strobe signal reception unit to generate a tracking clock signal, a clock reception unit to generate an internal clock signal, and a phase control unit to control the phase of the internal clock signal, ensuring data is sampled within the effective window even with timing variations, by tracking the strobe signal and compensating for phase shifts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the clock frequency is increased to achieve high-speed data transfer, then the data transfer speed is improved, but the timing accuracy of data sampling deteriorates due to clock signal delay and phase variations
Solution Approach 1:
The patent implements a feedback mechanism where the strobe signal (a delayed version of the clock signal) is fed back to the phase control unit. The phase control unit continuously adjusts the phase of the internal clock signal based on the strobe signal to maintain synchronization, ensuring that data sampling occurs at the optimal timing point even at high clock frequencies exceeding 1 GHz.
Solution Approach 2:
The patent makes the internal clock signal dynamic by allowing its phase to be continuously adjusted in real-time based on the strobe signal. This dynamic phase adjustment enables the system to adapt to timing variations and maintain sampling accuracy despite the high-speed operation and associated signal delays.
2Measurement precision
If the clock signal transmission path is simplified to reduce delay, then the timing accuracy is improved, but the circuit complexity for phase control increases
Solution Approach 1:
The strobe signal serves multiple functions: it acts as a timing reference for phase control, provides feedback for synchronization, and enables the phase adjustment mechanism. By making the strobe signal multi-functional, the patent avoids adding separate dedicated circuits for each function, thereby limiting the increase in overall circuit complexity while achieving accurate timing control.
3Reliability
If data training is extensively performed to improve reliability, then the data transfer reliability is improved, but the number of circuits and power consumption increase
Solution Approach 1:
The patent implements a self-adjusting mechanism where the phase control unit automatically adjusts the internal clock signal phase based on the strobe signal feedback during normal data transfer operations. This eliminates the need for extensive separate data training circuits and procedures, as the system continuously self-calibrates to maintain optimal timing and reliability without additional dedicated training hardware.
Data Source
AI summary
A semiconductor memory device includes: a strobe signal reception unit configured to receive a strobe signal and generate a tracking clock signal; a clock reception unit configured to receive a clock signal and generate an internal clock signal; a plurality of data reception units configured to receive parallel data in accordance with the internal clock signal and generate internal data; and a phase control unit configured to control the phase of the internal clock signal to track the tracking clock signal and to compensate for a variation in the phase of the internal clock signal while the data is received.