Memory Clock PLL Control for Uniform Frequency Matching
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Solution Overview
Problem
In information processing devices, clock noise can disrupt normal operation, and existing memory systems lack effective mechanisms to adjust clock frequencies uniformly, leading to potential operational issues.
Innovation Solution
A memory system incorporating a logic circuit and a phase locked loop (PLL) circuit that determines and adjusts the frequency of a clock signal to maintain uniformity, using a divider with an adjustable division ratio and controlling the PLL's power state based on frequency ratios between the clock and data signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the clock frequency is adjusted to match varying data signal frequencies, then the operational stability is improved, but the device complexity increases due to the need for frequency adjustment mechanisms
Solution Approach 1:
A logic circuit is introduced as an intermediary component that receives the data signal, determines its frequency, generates a control signal based on the frequency ratio between the clock signal and data signal, and controls the PLL circuit accordingly. This intermediary simplifies the overall control architecture while achieving frequency matching and operational stability.
2Adaptability or versatility
If a PLL circuit is used to generate the clock signal, then the frequency adjustment capability is improved, but the device complexity increases due to the additional circuit components
Solution Approach 1:
The division ratio of the PLL circuit is made dynamically adjustable based on the detected data signal frequency. The logic circuit continuously monitors the frequency ratio between the clock signal and data signal, and dynamically adjusts the PLL's division ratio to maintain the desired frequency relationship, enabling adaptability without permanent complex circuitry for all possible frequency combinations.
Solution Approach 2:
The invention changes the division ratio parameter of the PLL circuit based on the detected frequency characteristics of the data signal. By adjusting this key parameter dynamically, the system achieves frequency adaptability and operational stability without requiring complex fixed circuitry for all possible frequency scenarios.
3Measurement precision
If the division ratio of the PLL is adjusted dynamically, then the frequency matching precision is improved, but the control complexity increases
Solution Approach 1:
The logic circuit implements a feedback mechanism that continuously monitors the frequency relationship between the clock signal and data signal. Based on this feedback, it dynamically adjusts the division ratio of the PLL circuit to maintain precise frequency matching. This closed-loop feedback control achieves high precision frequency matching while keeping the control logic relatively simple and systematic.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The system ensures stable and normal operation by adjusting clock frequencies to match data signal frequencies, reducing the impact of noise and maintaining optimal performance across varying conditions.
Implementation Method 1
a phase locked loop (PLL) circuit. The logic circuit may determine a first frequency of a first clock using a first signal and may generate a second signal for adjusting the first frequency of the first clock. The PLL circuit may receive a second clock, and may generate the first clock having the first frequency determined by the logic circuit, using the second clock and the second signal.
Data Source
AI summary
A memory system includes a logic circuit and a phase locked loop (PLL) circuit. The logic circuit determines a first frequency of a first clock using a first signal and generates a second signal for adjusting the first frequency of the first clock. The PLL circuit receives a second clock, and generates the first clock having the first frequency determined by the logic circuit, using the second clock and the second signal. When a second frequency of the second clock varies, the logic circuit determines the first frequency of the first clock such that the first frequency of the first clock generated by the PLL circuit is uniform, and operates based on the first clock having the first frequency adjusted by the second signal.