Memory Clock Generation with Self-Timed Pulse Reset
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Solution Overview
Problem
Conventional memory designs face challenges in system-level cache memories due to multi-cycle memory access, excessive timing delays, and increased on-chip area consumption, necessitating improved clock generation operations for more efficient physical memory design implementations.
Innovation Solution
Implementing a novel clock generation scheme with integrated circuit components that generate and reset internal memory clocks using self-timed clocks (NGTP1, NGTP2) and logic circuits to control global timing pulses (GTP), allowing for improved memory access operations in system-level cache memories.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If additional buffers are added in the data path to address timing delays, then timing reliability is improved, but on-chip area consumption increases
Solution Approach 1:
The patent extracts the clock generation function from the traditional data path buffers and places it in a dedicated clock generation circuit. This separates the timing control function from the data transmission path, eliminating the need for additional buffers in the data path while maintaining timing reliability through dedicated clock signal generation and distribution.
Solution Approach 2:
The patent introduces a dedicated clock generation circuit as an intermediary between the system clock and the memory array. This intermediary generates precise timing signals (GTP, NGTP1, NGTP2) that control memory operations without requiring additional buffers in the data path, thus maintaining timing reliability while avoiding area penalty.
2Reliability
If additional buffers are added in the data path to address timing delays, then timing reliability is improved, but memory access performance deteriorates
Solution Approach 1:
The patent extracts the clock generation function from the data path and places it in a dedicated circuit, eliminating unnecessary buffers that would add timing delays. This maintains timing reliability while improving memory access performance by reducing the overall data path length and removing buffering overhead.
Solution Approach 2:
The patent implements preliminary clock signal generation and distribution before memory operations occur. By pre-generating and distributing timing signals (GTP, NGTP1, NGTP2) through dedicated clock trees, the system prepares timing control signals in advance, enabling faster and more reliable memory access without the need for additional buffers during data transmission.
3Device complexity
If conventional clock generation is used in system-level cache, then simplicity is maintained, but memory access efficiency deteriorates
Solution Approach 1:
The patent segments the clock generation into multiple independent components: a first clock generator for global timing pulses, a second clock generator for self-timed clocks, and a third clock generator for wordline control. This segmentation allows each clock signal to be optimized independently, improving memory access efficiency while keeping each individual generator relatively simple.
Solution Approach 2:
The patent implements dynamic clock generation where the timing signals are adjusted based on operational requirements. The clock generation circuit dynamically produces different timing signals (GTP for read operations, NGTP1/NGTP2 for write operations) based on the current memory access type, enabling optimized performance for each operation type while maintaining a unified clock generation approach.
Data Source
AI summary
Various implementations described herein are related to a device with a first clock generator that provides a first pulse signal based on a clock signal, wherein the first clock generator has a first tracking circuit that provides a first reset signal based on the first pulse signal. The device may include a second clock generator that provides a second pulse signal based on the clock signal, wherein the second clock generator has a second tracking circuit that provides a first control signal based on the second pulse signal. Also, the device may include a third clock generator that provides a third pulse signal based on the first reset signal, wherein the third clock generator has a logic circuit that provides a second control signal based on the third pulse signal.