Memory Interface Clock Gating With Delay-Adjusted Qualifier Timing
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Solution Overview
Problem
Existing memory interface circuits face challenges in efficiently capturing data due to inter-symbol interference (ISI) in high-frequency data strobe signals, leading to potential cycle-slip failures and invalid data capture, particularly in mobile devices using LPDDR SDRAM.
Innovation Solution
A memory interface circuit with a first and second receiver, a gating circuit, and a delay adjuster is employed to generate internal data strobe signals and qualifier signals, with a delay adjuster tuning the rise and fall times of the qualifier signal to align with the strobe signal, ensuring proper gating and data capture.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the memory interface circuit uses a conventional clock generation method without delay adjustment, then the circuit complexity is reduced, but the timing precision and data capture accuracy deteriorate due to inter-symbol interference in the preamble
Solution Approach 1:
The patent segments the clock generation process into multiple independent components: a first receiver for the differential data strobe signal, a second receiver for the qualifier signal, a delay adjuster for timing calibration, and a gating circuit for clock generation. This segmentation allows each component to be optimized independently, achieving precise timing control while maintaining modular circuit design.
Solution Approach 2:
The patent implements a training mode that performs preliminary delay calibration before normal data transmission. The delay adjuster is swept through different delay settings during training, and the optimal setting is selected based on timing requirements. This preliminary action ensures accurate timing alignment is established beforehand, eliminating the need for continuous complex adjustments during operation.
2Reliability
If the memory interface circuit implements precise delay adjustment for the qualifier signal, then the data capture accuracy is improved, but the device complexity increases due to additional components
Solution Approach 1:
The patent implements a feedback mechanism where the gate control circuit monitors the timing relationship between the internal data strobe signal and the qualifier signal. During training mode, the system sweeps through delay settings and selects the optimal delay value that satisfies timing requirements, creating a closed-loop feedback system that ensures reliable data capture without requiring overly complex continuous adjustment mechanisms.
Solution Approach 2:
The delay adjuster is configured to be swept automatically during a training phase, and the optimal delay setting is selected based on measured timing requirements. Once trained, the system operates autonomously with the selected delay setting, eliminating the need for continuous external intervention or complex real-time adjustment mechanisms, thus improving reliability without proportionally increasing complexity.
3Ease of manufacture
If the memory interface circuit uses a simple gating mechanism without delay adjustment, then the circuit is easier to manufacture, but the timing alignment between clock edges and data transitions is inaccurate
Solution Approach 1:
The patent introduces a programmable delay adjuster that modifies the delay parameter of the qualifier signal based on training results. This allows the timing alignment precision to be adjusted as a configurable parameter rather than being fixed by manufacturing tolerances alone. The delay setting can be optimized for different process variations, achieving precise timing alignment while using standard manufacturing processes.
4Productivity
If the memory interface circuit implements comprehensive delay adjustment and training, then the productivity and data integrity are improved, but the training time and operational overhead increase
Solution Approach 1:
The patent implements delay adjustment and training only during an initial training mode before normal operation begins. Once the optimal delay setting is determined during training, the system operates in normal mode using this pre-determined setting without requiring continuous training. This partial application of the training process achieves the necessary timing precision while minimizing the time overhead, as the training occurs only once rather than continuously.
Data Source
AI summary
A method for operating a memory interface circuit includes generating an internal data strobe signal based on a first data strobe signal and a second data strobe signal using a first receiver, generating a qualifier signal based on the second data strobe signal and a reference voltage using a second receiver, delaying a rise time and a fall time of the qualifier signal using a delay adjuster, generating a gate control signal based on the internal data strobe signal and the qualifier signal after the delay adjuster, and gating a portion of the internal data strobe signal based on the gate control signal to provide a read clock signal.