Memory Clock Processing for Duty-Cycle Distortion Read Latching
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Solution Overview
Problem
In semiconductor memory technologies, the distortion of clock signals during duty cycle adjustment in memories leads to incorrect data retrieval by CPUs, causing failures in duty cycle adjustment.
Innovation Solution
A memory with a clock processing circuit that includes a duty cycle module, a clock generation module, a data strobe generation module, and a selection module. The circuit adjusts the duty cycle of an external data clock signal, generates a read clock signal and a read data strobe signal, and selects either signal as a target read data strobe signal to ensure correct data latching, even in cases of duty cycle distortion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the memory adjusts the duty cycle of the clock signal, then the clock signal can be optimized for performance, but the clock signal becomes distorted causing incorrect data retrieval
Solution Approach 1:
The patent introduces a mode register as an intermediary component that stores the duty cycle parameter separately from the clock signal transmission path. This allows the CPU to read the duty cycle parameter through the mode register without the distorted clock signal interfering with the data retrieval process, thus resolving the contradiction between clock signal optimization and data retrieval accuracy
Solution Approach 2:
The patent separates the duty cycle adjustment function from the data transmission function by implementing independent reading paths. The duty cycle parameter is read through the mode register while data is read through the normal data bus, allowing both functions to operate independently without mutual interference despite the distorted clock signal
2Adaptability or versatility
If the CPU reads the duty cycle parameter from the mode register during clock signal adjustment, then the duty cycle can be configured, but the distorted read clock signal causes wrong data to be obtained
Solution Approach 1:
The mode register serves as an intermediary that decouples the duty cycle parameter storage from the distorted clock signal path. The CPU can reliably read the duty cycle parameter through this intermediary register without being affected by the clock signal distortion, ensuring both configurability and reading accuracy
3Ease of operation
If the memory outputs both read clock signal and read data signal, then data latching can be performed, but the distorted clock signal causes latching failures
Solution Approach 1:
The patent uses the mode register as an intermediary to provide an alternative, reliable path for obtaining the duty cycle parameter. This intermediary mechanism ensures that even when the read clock signal is distorted and causes latching failures, the system can still successfully configure and read the duty cycle parameter through the mode register
Data Source
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AI summary
A memory, a control apparatus, a clock processing method, and an electronic device are provided. A clock processing circuit in the memory includes: a duty cycle module, configured to adjust a duty cycle of a data clock signal to output an internal clock signal; a first clock generation module, configured to receive the internal clock signal, and output a first read clock signal based on the internal clock signal, the first read clock signal being a pulse signal; a second clock generation module, configured to generate and output a second read clock signal, the second read clock signal having only one level state change edge; and a selection module, configured to receive the first read clock signal and the second read clock signal, and output one of the first read clock signal and the second read clock signal as a target read clock signal.