Memory Clock Relocking Circuit for Skew and Duty Error Correction
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Solution Overview
Problem
Semiconductor memory devices face challenges in synchronizing clock signals due to internal circuit delays, leading to time delays and duty errors, which affect data transfer efficiency and accuracy.
Innovation Solution
A semiconductor memory device with a quadrature error correction circuit that generates corrected clock signals with a 90-degree phase difference by adjusting skew and duty errors, and performs relocking operations in response to a relock signal to maintain synchronization, enhancing performance and responsiveness to operating condition changes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a circuit is used to compensate for time delay and correct duty error, then clock signal synchronization is improved, but device complexity increases
Solution Approach 1:
The quadrature error correction circuit dynamically adjusts skew and duty error parameters based on detected errors, rather than using fixed compensation circuits. The circuit switches between different operation modes (locking and relocking) to adaptively correct synchronization errors, reducing the need for complex static compensation circuitry.
Solution Approach 2:
The invention changes the approach from complex circuit-based compensation to parameter-based correction. By adjusting skew and duty error parameters through the quadrature error correction circuit, the patent achieves synchronization without requiring complex additional circuits, thus improving reliability while controlling complexity.
2Measurement precision
If the quadrature error correction circuit performs continuous locking operation, then clock signal accuracy is maintained, but power consumption increases
Solution Approach 1:
The quadrature error correction circuit performs relocking operations periodically based on relock signals rather than continuously. The circuit switches between locking operation mode and relocking operation mode, maintaining clock signal accuracy through periodic corrections while reducing power consumption by avoiding continuous operation.
Solution Approach 2:
The circuit maintains clock signal accuracy through continuous monitoring but performs corrective actions only when needed (upon receiving relock signals). This approach ensures continuous useful action in terms of accuracy maintenance while minimizing energy-consuming operations to only when necessary.
3Productivity
If the semiconductor memory device responds quickly to operating condition changes, then productivity is improved, but reliability may deteriorate due to rushed synchronization
Solution Approach 1:
The quadrature error correction circuit performs preliminary locking operations to establish baseline synchronization before actual data operations. When relock signals are received indicating condition changes, the circuit can quickly perform relocking operations based on the pre-established locking framework, enabling fast response while maintaining reliability through the preliminary synchronization work.
Data Source
AI summary
A semiconductor memory device includes a quadrature error correction circuit, a clock generation circuit and a data input/output (I/O) buffer. The quadrature error correction circuit performs a locking operation to generate a first corrected clock signal and a second corrected clock signal by adjusting a skew and a duty error of a first through fourth clock signals generated based on a data clock signal and performs a relocking operation to lock the second corrected clock signal to the first corrected clock signal in response to a relock signal. The clock generation circuit generates an output clock signal and a strobe signal based on the first corrected clock signal and the second corrected clock signal. The data I/O buffer generates a data signal by sampling data from a memory cell array based on the output clock signal and transmits the data signal and the strobe signal to a memory controller.


