Memory Clock Division Correction for Resume Data Alignment
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Solution Overview
Problem
Memory devices face synchronization issues after resuming operation from an interrupted state, leading to deserialization of data out of order due to changes in the clock dividing start time point, affecting performance and data integrity.
Innovation Solution
A memory device with an internal clock generator, deserializer, and clock controller that corrects the clock dividing start time point by comparing deserialized data with reference data, using multiple internal clock signals with different phases to ensure accurate synchronization and data alignment.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the memory device enters an interrupt mode and exits to resume operation, then the operation can be interrupted and resumed, but the clock signal synchronization between the memory device and host becomes misaligned
Solution Approach 1:
The patent implements a feedback mechanism where the memory device monitors the clock signal from the host and automatically adjusts its internal clock dividing start time point based on the detected synchronization status. The clock controller continuously compares the phase and timing of received clock signals with internal clock signals, and when desynchronization is detected after interrupt mode, the system generates control signals to realign the clock dividing start time point, ensuring continuous synchronization without manual intervention
Solution Approach 2:
The patent applies preliminary action by initializing and adjusting the clock dividing start time point before the memory device enters interrupt mode. The system pre-configures the clock circuit settings and establishes synchronization baseline data before interruption occurs, so that when the device resumes operation, the pre-established timing reference enables faster and more accurate re-synchronization compared to starting from an uninitialized state
2Ease of operation
If the clock dividing start time point is not corrected after interrupt mode, then the device can operate independently, but data deserialization occurs out of order affecting data integrity
Solution Approach 1:
The patent uses feedback control where the deserialized data is continuously monitored and compared against expected data patterns. When data alignment errors are detected due to incorrect clock dividing start time point, the system generates feedback signals to the clock controller, which automatically adjusts the timing to realign data serialization, ensuring data integrity while maintaining independent operation capability
Solution Approach 2:
The patent replaces manual or hardware-level mechanical clock adjustment mechanisms with software-based digital signal processing. The clock controller uses digital logic to detect synchronization status and dynamically adjust the clock dividing start time point through programmable timing control, enabling precise data alignment without complex hardware modifications while maintaining operational independence
3Measurement precision
If multiple internal clock signals with different phases are used for deserialization, then data alignment accuracy is improved, but the device complexity increases
Solution Approach 1:
The patent segments the clock signal generation into multiple independent phases, where each internal clock signal operates at a different phase angle (e.g., 0°, 90°, 180°, 270°). This segmentation allows the deserializer to select the appropriate phase for sampling data, improving alignment accuracy. Each phase-separated clock signal is generated using dedicated but simplified circuitry, distributing the complexity across modular components rather than requiring a single complex clock generation system
Data Source
AI summary
A memory device includes an internal clock generator, a deserializer, a data comparator, and a clock controller. The internal clock generator generates a plurality of internal clock signals, which have different phases from each other, by dividing a clock signal received from a host. The deserializer deserializes serial test data received from a host as pieces of internal data using the internal clock signals. The data comparator compares reference data with the internal data. The clock controller corrects a clock dividing start time point of the clock signal of the internal clock generator based on the result of the comparison of the reference data and the internal data.