Memory Clock Mode Switching for Serial Ring Flash Arrays
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Solution Overview
Problem
The existing flash memory systems face performance limitations due to signal integrity issues such as crosstalk, signal skew, and simultaneous switching noise, as well as increased power consumption and clock distribution challenges as the number of memory devices connected in parallel increases, limiting the system's ability to accommodate high-speed operation and large storage capacities.
Innovation Solution
A semiconductor device with a configurable input circuit that can operate in modes for receiving coincident or non-coincident clock and data edges, allowing for serial connection of memory devices in a ring topology configuration, which reduces signal degradation and power consumption while enabling high-speed operation by using a clock switch and mode setter to manage clock signals and data input/output buffers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple memory devices are connected in parallel to increase storage capacity, then the available storage capacity increases, but signal integrity deteriorates due to crosstalk, signal skew, and simultaneous switching noise
Solution Approach 1:
The patent segments the parallel memory device connection into a serial ring topology where memory devices are connected in a daisy-chain fashion. This segmentation eliminates the simultaneous switching of multiple devices on common buses, thereby reducing crosstalk, signal skew, and noise while maintaining increased storage capacity through the addition of more devices in the ring.
Solution Approach 2:
The patent transitions from a traditional parallel bus architecture to a serial ring topology, changing the dimensional arrangement of data flow. Instead of multiple devices sharing common data and address buses in parallel, data flows sequentially through the ring in a single dimension, eliminating the interference issues inherent in parallel configurations.
2Quantity of substance
If multiple memory devices are connected in parallel to increase storage capacity, then the available storage capacity increases, but power consumption increases due to frequent charging and discharging of signal tracks
Solution Approach 1:
By segmenting the parallel connection into a serial ring topology, the patent eliminates the need for frequent charging and discharging of common signal tracks that occurs in parallel configurations. Each device in the ring communicates sequentially, reducing the overall power consumption while maintaining the ability to scale storage capacity by adding more devices to the ring.
3Speed
If the clock frequency is increased to improve operation speed, then the processing speed increases, but signal integrity issues such as crosstalk and simultaneous switching noise worsen
Solution Approach 1:
The patent changes the architecture from parallel to serial ring topology, enabling high-speed operation without the signal integrity issues that plague high-frequency parallel systems. The serial nature of the ring allows for higher clock frequencies because there is no simultaneous switching of multiple devices on common buses, thereby eliminating crosstalk and noise problems while achieving fast processing speeds.
4Quantity of substance
If additional channels are added to accommodate more memory devices, then the storage capacity increases, but device complexity increases
Solution Approach 1:
The patent employs a universal ring topology where a single data path serves multiple memory devices sequentially. Instead of requiring additional dedicated channels for each device as in parallel architectures, the same data and address buses are reused by different devices at different times as data circulates through the ring, thereby increasing storage capacity without increasing the number of physical channels or buses required.
Data Source
AI summary
A clock mode configuration circuit for a memory device is described. A memory system includes any number of memory devices serially connected to each other, where each memory device receives a clock signal. The clock signal can be provided either in parallel to all the memory devices or serially from memory device to memory device through a common clock input. The clock mode configuration circuit in each memory device is set to a parallel mode for receiving the parallel clock signal, and to a serial mode for receiving a source synchronous clock signal from a prior memory device. Depending on the set operating mode, the data input circuits will be configured for the corresponding data signal format, and the corresponding clock input circuits will be either enabled or disabled. The parallel mode and the serial mode is set by sensing a voltage level of a reference voltage provided to each memory device.