Memory Clock Mode Switching for Serial Flash Ring Topologies
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Solution Overview
Problem
The existing parallel configuration of Flash memory systems faces performance limitations due to signal integrity issues such as crosstalk, signal skew, and simultaneous switching noise, leading to increased power consumption and clock performance problems, which restrict the number of memory devices that can be connected effectively.
Innovation Solution
A semiconductor device with a configurable input circuit that operates in modes for receiving coincident or non-coincident clock and data edges, allowing for shifted clock edges within a data valid window, and a memory system with a ring topology configuration where memory devices are serially connected, enabling the use of either parallel or serial clock signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple memory devices are connected in parallel to increase storage capacity, then the available storage capacity increases, but signal integrity is degraded by crosstalk, signal skew, and simultaneous switching noise
Solution Approach 1:
The system segments the parallel memory device connections into serial connections arranged in a ring topology. Instead of connecting all memory devices in parallel to a single controller, the devices are connected in series forming a closed loop, with each device communicating sequentially with adjacent devices. This segmentation eliminates the signal integrity issues caused by parallel connections while maintaining the ability to access multiple devices.
Solution Approach 2:
The invention transitions from a two-dimensional parallel connection architecture (multiple devices connected simultaneously to a controller via shared buses) to a one-dimensional serial ring topology (devices connected in sequence forming a closed loop). This dimensional change fundamentally alters the signal transmission path, eliminating crosstalk and simultaneous switching noise inherent in parallel architectures.
2Quantity of substance
If the number of memory devices connected in parallel increases, then the storage capacity increases, but power consumption increases due to frequent charging and discharging of signal tracks
Solution Approach 1:
The parallel signal tracks are segmented into serial communication paths. Instead of simultaneously charging and discharging multiple parallel signal lines, the system uses sequential serial communication where data is transmitted one bit at a time through dedicated point-to-point connections, significantly reducing the total capacitance that must be charged and discharged.
Solution Approach 2:
The invention changes the fundamental parameter of signal transmission from parallel voltage-level signaling (requiring frequent charging/discharging of large capacitances) to serial differential signaling with lower voltage swings. This parameter change reduces the energy consumed per bit transmission and eliminates the simultaneous switching noise that causes excessive power consumption.
3Speed
If the system clock frequency is increased to improve operation speed, then the processing speed increases, but clock performance issues arise due to extensive clock distribution in parallel configuration
Solution Approach 1:
The clock signal is extracted from the extensive parallel distribution network and replaced with serial clocking mechanisms. Each memory device in the ring topology has its own local clocking, eliminating the need for a centralized clock distribution system that suffers from skew and integrity issues at high frequencies.
Solution Approach 2:
The clock distribution architecture transitions from a two-dimensional parallel broadcast (single clock source distributing to all devices simultaneously) to a one-dimensional serial progression (clock signals propagating sequentially around the ring). This dimensional change eliminates clock skew issues while enabling high-speed operation.
4Quantity of substance
If more memory devices are connected in parallel, then the storage capacity increases, but the number of chip enable signals required increases, increasing controller complexity and cost
Solution Approach 1:
The ring topology provides a universal interface that handles both address and data transmission through the same serial communication path. Instead of requiring separate control lines (chip enable, address, data) for each parallel device, the serial ring uses a unified protocol where the same communication channel serves multiple functions, reducing controller complexity.
Solution Approach 2:
The invention changes the control mechanism from multiple discrete control signals (chip enable, address, write, read) to a single serial communication stream with embedded control information. This parameter change consolidates multiple control functions into a unified protocol, significantly reducing the number of controller I/O requirements.
Data Source
Figure 1
Figure 2A~2B
Figure 3A
AI summary
A clock mode configuration circuit for a memory device is described. A memory system includes any number of memory devices serially connected to each other, where each memory device receives a clock signal. The clock signal can be provided either in parallel to all the memory devices or serially from memory device to memory device through a common clock input. The clock mode configuration circuit in each memory device is set to a parallel mode for receiving the parallel clock signal, and to a serial mode for receiving a source synchronous clock signal from a prior memory device. Depending on the set operating mode, the data input circuits will be configured for the corresponding data signal format, and the corresponding clock input circuits will be either enabled or disabled. The parallel mode and the serial mode is set by sensing a voltage level of a reference voltage provided to each memory device.