Semiconductor Memory Device Clock Signal Division and Sampling
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Solution Overview
Problem
DDR4 semiconductor memory systems face limitations due to a large number of external terminals and inability to operate at frequencies beyond a certain threshold, necessitating a solution for efficient command and address signal processing and on-die termination management.
Innovation Solution
A semiconductor memory device and memory system that employs a frequency divider to generate phase-inverted clock signals, samplers for chip selection and command/address processing, a signal detector, control circuit, and flag signal generator to decode commands and manage on-die termination resistors, optimizing terminal usage and frequency operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If DDR4 memory uses on-die termination terminal with on-die termination control signal, then termination control is improved, but the number of external terminals increases
Solution Approach 1:
The patent combines the termination control signal with the command and address signal by sampling the termination control signal at the same time as sampling command and address signals using the same sampler circuit. This merging approach allows the termination control functionality to be achieved without requiring separate external terminals, thereby reducing the total number of external terminals while maintaining reliable termination control.
2Speed
If DDR4 memory operates at higher clock frequencies, then data transfer speed is improved, but the system cannot operate beyond a certain threshold frequency
Solution Approach 1:
The patent employs dynamic sampling techniques where the sampler circuits sample signals at specific phases of the clock cycle. By dynamically adjusting when sampling occurs relative to the clock edge and using phase-inverted clock signals, the system can operate at higher frequencies while maintaining signal integrity and operational stability. The dynamic nature of the sampling approach allows the system to adapt to higher clock frequencies without exceeding reliability thresholds.
3Measurement precision
If command and address signals are processed with high precision sampling, then signal accuracy is improved, but power consumption increases
Solution Approach 1:
The patent uses periodic sampling where the sampler circuits sample command and address signals at specific periodic intervals synchronized with the clock signal phases. This periodic action allows for high-precision signal capture only when necessary (at critical sampling points), rather than continuous high-precision processing, thereby maintaining signal accuracy while reducing overall power consumption compared to continuous high-precision processing.
Data Source
AI summary
A semiconductor memory device divides a clock signal to generate a first clock signal and a second clock signal, outputs a chip selection signal as a first chip selection signal in response to the first clock signal, outputs the buffered chip selection signal as a second chip selection signal in response to the second clock signal, outputs the first chip selection signal as a third chip selection signal in response to the second clock signal, outputs a buffered command and address as a first command and address in response to the first clock signal, outputs the buffered command and address as a second command and address in response to the second clock signal, outputs the first chip selection signal as a first selection signal in response to the first clock signal, and outputs the third chip selection signal as a second selection signal in response to the second clock signal.