Memory Clock Scaling for SoC Bus Traffic Distribution
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Solution Overview
Problem
The bottleneck phenomenon in bus traffic within system-on-chip (SoC) products, particularly in memory controllers, leads to performance degradation, and existing solutions to enhance bus clock frequency or bandwidth are limited by increased power consumption and hardware constraints, especially when using low-power processors.
Innovation Solution
A bus system with time-sharing of internal memory by scaling the memory clock connected to multiple slave ports, allowing for dynamic adjustment of memory clock frequency based on traffic demand, thereby distributing bus traffic without increasing the bus clock frequency and minimizing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the bus clock frequency is enhanced to overcome the bottleneck phenomenon in memory controllers, then the bus bandwidth and performance are improved, but the power consumption of the entire system is increased
Solution Approach 1:
The patent applies dynamic clock frequency adjustment by introducing a bus clock frequency scaling mechanism that adapts the memory controller's clock frequency based on actual traffic conditions. The bus clock frequency is dynamically scaled up or down according to the workload demand, allowing the system to achieve high bandwidth when needed while consuming minimal power during low-traffic periods, thus resolving the contradiction between performance and power consumption
Solution Approach 2:
The patent changes the clock frequency parameter dynamically rather than maintaining a fixed high frequency. By scaling the bus clock frequency based on traffic conditions, the system can achieve the necessary bandwidth improvements while avoiding continuous high power consumption, effectively resolving the contradiction between productivity and energy usage
2Productivity
If the bus bandwidth is expanded to overcome the bottleneck phenomenon, then the performance is improved, but the hardware design and configuration are limited
Solution Approach 1:
Instead of expanding hardware bandwidth through additional physical channels or wider data buses, the patent achieves bandwidth improvement by changing the temporal parameter of clock frequency. This software-controlled frequency scaling approach avoids the hardware complexity and design limitations associated with physical bandwidth expansion, providing a more flexible and scalable solution
Data Source
AI summary
A bus system is proposed, which includes M (M is a natural number) master ports, N (N is a natural number) slave ports, a bus, A (A is a natural number) masters, B (B is a natural number) salves, and an internal memory. The bus system includes P (P is a natural number, P≤M) master ports, a traffic monitoring unit, Q (Q is a natural number, Q≤N) slaves, a port traffic monitoring unit, and a memory clock scaling unit. Accordingly, in a system-on-chip using a low-power processor, a memory clock of an internal memory connected to a plurality of slave ports is scaled so as to distribute bus traffic.