Memory System Clock Signal Segmentation for Independent Frequency Operation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional memory systems rely on differential clock signals for both memory devices, limiting flexibility and potentially causing mismatched operating frequencies and phase differences, which can affect the accessing speeds of memory devices.
Innovation Solution
The memory system introduces mode registers that allow memory devices to operate using single-ended clock signals, enabling independent frequencies and phase relationships between clock signals, allowing each device to transmit or receive data based on its specific mode settings.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If differential clock signals are used for both memory devices, then signal integrity and synchronization are improved, but flexibility and adaptability of operating frequencies are reduced
Solution Approach 1:
The patent segments the clock signal distribution by providing separate clock signal paths for each memory device. The memory controller can independently configure clock signals for different memory devices, allowing each device to operate at its optimal frequency without being constrained by a shared differential clock pair.
Solution Approach 2:
The patent introduces dynamic configurability where memory devices can be set to different operating modes (differential or single-ended) through mode registers. This allows the system to adapt clock signal configurations dynamically based on the specific requirements of each memory device, achieving both reliability and flexibility.
2Stability of the object's composition
If differential clock signals with fixed phase difference are used, then synchronization between memory devices is improved, but mismatched operating frequencies and phase differences are caused when devices have different accessing speeds
Solution Approach 1:
The patent applies local quality by allowing each memory device to have its own clock signal characteristics tailored to its specific performance requirements. Fast memory devices can operate at higher frequencies with optimized phase relationships, while slower devices operate at lower frequencies, with each device's clock configuration independently optimized for its accessing speed.
Solution Approach 2:
The patent enables parameter changes by allowing the memory controller to independently adjust clock frequency and phase parameters for each memory device. Mode registers in each memory device store configuration information that determines the operating mode and timing parameters, enabling the system to match clock parameters to the actual accessing speeds of different memory devices.
3Device complexity
If shared clock signals are used for multiple memory devices, then device complexity is reduced, but the ability to operate at different accessing speeds is limited
Solution Approach 1:
The patent achieves universality by designing a clock signal distribution system that can accommodate multiple operating modes. The same clock signal infrastructure supports both differential and single-ended modes, and can serve memory devices with different speed requirements, making the system universally applicable to diverse memory configurations without increasing complexity.
Data Source
AI summary
A memory system includes a memory controller, a first memory device and a second memory device. The memory controller issues a first clock signal and a second clock signal. The memory controller transmits or receives a data signal. The first memory device receives the first clock signal and the second clock signal. The second memory device receives the first dock signal and the second clock signal. If a first mode register of the first memory device is in a first single-ended mode and a second mode register of the second memory device is in a second single-ended mode, the first memory device transmits or receives the data signal according to the first dock signal, and the second memory device transmits or receives the data signal according to the second clock signal.