Memory Clock Selection Circuit for High-Frequency Stability
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Solution Overview
Problem
High-frequency semiconductor memory apparatuses are sensitive to clock frequency distortions, leading to erroneous operations, and require a stable clock to prevent such issues, especially when using high-frequency clocks.
Innovation Solution
A clock generation circuit with an internal clock generation unit and a clock selection unit that selectively outputs either the input clock or a Phase Locked Loop (PLL) clock based on selection signals, ensuring stability and flexibility according to user requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a high-frequency clock is used to increase operating speed, then productivity is improved, but the clock becomes more sensitive to distortion and reliability deteriorates
Solution Approach 1:
The clock system is segmented into multiple independent clock sources (external clock input and internal PLL clock generation). This allows the system to divide the clock supply function between different sources, using the external clock for low-frequency stable operation and the internal PLL for high-frequency generation, thereby resolving the contradiction between speed and stability
Solution Approach 2:
The clock selection is made dynamic through a clock selection unit that can switch between external clock and internal PLL clock based on operating conditions. This dynamic adaptation allows the system to select the most appropriate clock source for each operating mode, achieving both high speed when needed and high stability when required
2Device complexity
If a single clock is used for all internal circuits, then device complexity is reduced, but clock distortion increases when multiple circuits use the same clock
Solution Approach 1:
The clock distribution is segmented into separate paths: one path uses the external clock for data input/unit operations, and another path uses the internal PLL-generated clock for data output unit operations. This segmentation prevents mutual interference and waveform distortion that would occur if all circuits shared a single clock source, while maintaining relatively simple overall structure
3Reliability
If an internal PLL clock is always used to ensure stability, then reliability is improved, but power consumption increases
Solution Approach 1:
The clock system dynamically adjusts its operation mode based on frequency requirements. When high-frequency operation is needed, the PLL is activated to generate the internal clock; when low-frequency operation suffices, the system switches to using the external clock directly. This dynamic control allows the system to maintain reliability when needed while minimizing power consumption during normal operation
Solution Approach 2:
The system changes the operating parameter (clock frequency) by selecting different clock sources. The external clock is used for low-frequency operations to save power, while the internal PLL is engaged for high-frequency operations where its stability is essential. This parameter-based selection optimizes the trade-off between power consumption and reliability
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution provides stable operation and reduced power consumption by allowing selective use of the PLL clock or input clock, improving reliability and enabling operation according to frequency and user needs.
Implementation Method 1
an internal clock generation unit that receives a clock and generates an internal clock
Data Source
AI summary
A clock generation circuit for a semiconductor memory apparatus includes an internal clock generation unit that receives a clock and generates an internal clock, and a clock selection unit that selectively outputs the clock or the internal clock in response to a selection signal.