Memory Clock Mode Switching for Serial Flash Signal Integrity
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Solution Overview
Problem
The existing parallel configuration of Flash memory systems faces performance limitations due to signal integrity issues like crosstalk, signal skew, and simultaneous switching noise, leading to increased power consumption and limitations in the number of memory devices that can be connected, which restricts high-speed operation and storage capacity.
Innovation Solution
A serially connected memory system with a ring topology configuration, where memory devices are connected in series, allowing for the use of either parallel or serial clock signals, and a configurable clock mode circuit that adjusts based on a reference voltage to optimize data and clock signal formats for high-speed operation while minimizing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory devices are connected in parallel configuration, then storage capacity is increased, but signal integrity deteriorates due to crosstalk, signal skew, and simultaneous switching noise
Solution Approach 1:
The parallel configuration is segmented into multiple serial channels, where data is transmitted sequentially through different memory devices rather than simultaneously through shared buses. This segmentation eliminates crosstalk and signal skew by providing dedicated transmission paths for each device.
Solution Approach 2:
The invention inverts the traditional parallel architecture by adopting a serial connection topology. Instead of connecting multiple memory devices in parallel to a common bus, devices are connected in series, with each device having dedicated input and output paths, thereby eliminating the harmful effects of parallel signal interference.
2Productivity
If clock frequency is increased to achieve higher data rates, then productivity is improved, but power consumption increases
Solution Approach 1:
The invention changes the fundamental parameter of data transmission from parallel to serial, allowing high data rates to be achieved through increased bit depth and sequential processing rather than through increased clock frequency. This parameter change enables high productivity with lower power consumption by utilizing efficient serial transmission protocols and reduced signal switching.
3Quantity of substance
If the number of memory devices is increased in parallel configuration, then storage capacity is increased, but device complexity increases due to additional channels and control signals
Solution Approach 1:
The serial configuration provides universal functionality where a single channel can access multiple memory devices sequentially. The same data bus and control signals are reused for each device in the chain, eliminating the need for separate channels and control logic for each device, thereby reducing overall system complexity while maintaining expanded storage capacity.
Data Source
AI summary
A clock mode configuration circuit for a memory device is described. A memory system includes any number of memory devices serially connected to each other, where each memory device receives a clock signal. The clock signal can be provided either in parallel to all the memory devices or serially from memory device to memory device through a common clock input. The clock mode configuration circuit in each memory device is set to a parallel mode for receiving the parallel clock signal, and to a serial mode for receiving a source synchronous clock signal from a prior memory device. Depending on the set operating mode, the data input circuits will be configured for the corresponding data signal format, and the corresponding clock input circuits will be either enabled or disabled. The parallel mode and the serial mode is set by sensing a voltage level of a reference voltage provided to each memory device.