Memory Clock Buffering With Multi-Phase Skew Correction
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Solution Overview
Problem
Semiconductor devices face issues with clock signal distortion and phase skew, leading to decreased setup and hold margins in data sampling, which affects the reliability of clock signals within the devices.
Innovation Solution
A memory device and system that includes a first buffer to generate an internal clock signal from an external clock signal, and a processing circuitry to generate multiple internal clock signals with different phases, which corrects skew and duty cycle distortions, ensuring reliable data transmission.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If clock signals are transferred through semiconductor device, then data transmission is enabled, but phase skew and duty cycle distortion occur
Solution Approach 1:
The clock signal transmission path is segmented into multiple independent buffer stages (first buffer, second buffer, third buffer) rather than using a single long transmission path. Each buffer independently regenerates the clock signal, preventing cumulative phase skew and duty cycle distortion across the entire transmission path.
Solution Approach 2:
The first buffer performs preliminary clock signal regeneration at the input stage, establishing a clean reference clock signal before it enters the data transmission path. This preliminary action prevents distortion from propagating through subsequent stages.
2Productivity
If multiple phase clock signals are used for data sampling, then data transmission capability is improved, but setup margin and hold margin decrease
Solution Approach 1:
Each buffer stage provides localized clock signal regeneration with optimized characteristics for its specific position in the transmission path. The first buffer optimizes for input coupling, the second buffer optimizes for mid-path transmission, and the third buffer optimizes for output delivery, ensuring each segment has the appropriate clock signal quality for its function.
Data Source
AI summary
A memory device in which reliability of a clock signal is improved is provided. The memory device comprises a data module including a clock signal generator configured to receive an internal clock signal from a buffer, and to generate a first internal clock signal, a second internal clock signal, a third internal clock signal, and a fourth internal clock signal having different phases, on the basis of the internal clock signal, and a first data signal generator configured to generate a first data signal on the basis of first data and the first internal clock signal, generate a second data signal on the basis of second data and the second internal clock signal, generate a third data signal on the basis of third data and the third internal clock signal, and generate a fourth data signal on the basis of fourth data and the fourth internal clock signal.