Multi-Phase Memory Clock Training for Skew Alignment
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Solution Overview
Problem
Memory devices experience errors during data transmission and reception due to skew in multi-phase clock signals, particularly at higher speeds, which existing technologies fail to accurately adjust.
Innovation Solution
A memory device and controller system that includes a multi-phase clock generator, monitoring clock signal generator, duty adjuster, and skew adjuster to detect and adjust skews through a training process involving multiple steps with monitoring clock signals and control codes to synchronize clock signals accurately.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If multi-phase clock signals are used for high-speed data transmission, then transmission speed is improved, but skew between clock phases causes errors in data transmission and reception
Solution Approach 1:
The patent performs skew detection and adjustment during a training operation before normal data transmission begins. The monitoring clock signal generator creates test patterns and the duty detector measures skew in advance, allowing the skew adjuster to pre-correct clock phase alignments before actual high-speed data communication starts, thus ensuring reliability at high speeds
Solution Approach 2:
The patent implements a feedback mechanism where the duty detector continuously monitors the skew between multi-phase clock signals and provides measurement results to the skew adjuster. The skew adjuster uses this feedback information to dynamically adjust clock signal phases, creating a closed-loop control system that maintains accurate timing even during high-speed operation
2Measurement precision
If skew adjustment is performed during training operation, then clock signal accuracy is improved, but training time and initialization complexity increase
Solution Approach 1:
The patent segments the skew detection and adjustment process into multiple distinct steps: generating monitoring clock signals with specific data patterns, detecting duty cycles at different phase points, calculating skew amounts for different clock pairs, and applying adjustments. This segmentation allows for systematic and efficient calibration, reducing overall training time while maintaining precision
Solution Approach 2:
The patent changes operational parameters during the training operation, including switching between different data patterns (e.g., alternating 1s and 0s), adjusting monitoring clock signal frequencies, and modifying phase detection points. These parameter variations enable comprehensive skew measurement across different operating conditions, achieving high accuracy without requiring excessively long training periods
3Measurement precision
If multiple monitoring clock signals are generated for different phase detections, then skew detection accuracy is improved, but device complexity increases
Solution Approach 1:
The monitoring clock signal generator is designed as a universal circuit that can generate multiple types of monitoring clock signals with different data patterns and phase relationships using the same hardware structure. This multi-functional design allows comprehensive skew detection across all clock phases without requiring separate dedicated circuits for each measurement type, thus limiting the increase in device complexity
Data Source
AI summary
A memory device includes a multi-phase clock generator configured to generate first to N-th clock signals having N different phases based on a clock signal from the memory controller, and a monitoring clock signal generator configured to generate a monitoring clock signal having a logic state corresponding to a data pattern in synchronization with edges of the first to N-th clock signals, wherein the monitoring clock signal includes a first monitoring clock signal configured to detect a skew between the first and third clock signals in a first step of a training operation, a second monitoring clock signal configured to detect a skew between the second and fourth clock signals in a second step of the training operation, and a third monitoring clock signal configured to detect a skew between the first and second clock signals in a third step of the training operation.