Memory Clock Frequency Slew Control for DLL Relocking
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Solution Overview
Problem
Existing clock frequency change techniques in memory subsystems often disrupt normal operations, particularly in real-time applications, due to abrupt changes that can malfunction downstream components like DLLs, and fail to manage power consumption effectively during frequency shifts.
Innovation Solution
A system that iteratively changes the clock frequency through a slew operation using a phase-lock loop (PLL), allowing for intermediate frequency adjustments without interrupting normal memory operations, and ensures DLLs relock by pausing operations and using self-refresh modes or explicit resets, enabling seamless transitions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If the clock frequency is abruptly changed to reduce power consumption, then power savings are achieved, but downstream DLLs may malfunction and memory operations are disrupted
Solution Approach 1:
The clock frequency change process is segmented into multiple discrete steps rather than a single abrupt change. The frequency is adjusted through intermediate values, allowing DLLs to track and adapt to each step, thereby preventing malfunction while achieving power savings.
Solution Approach 2:
The system dynamically adjusts the clock frequency based on operational conditions. The frequency scaling is performed adaptively, with the ability to pause at intermediate frequencies if DLL relocking is required, ensuring continuous reliable operation while optimizing power consumption.
2Reliability
If the clock frequency is gradually changed through slew operation to maintain DLL tracking, then reliability is improved, but the frequency change time increases and may conflict with DLL phase-tracking range
Solution Approach 1:
The frequency change is performed as a periodic slew operation with controlled steps. The system periodically adjusts the frequency in manageable increments, allowing DLLs to track each change while maintaining overall progress toward the target frequency, balancing speed and reliability.
Solution Approach 2:
The system monitors DLL lock status during frequency changes and provides feedback to control the slew rate. If DLL tracking is detected to be at risk, the system adjusts the frequency change rate or pauses to allow relocking, ensuring reliable operation while minimizing total change time.
3Reliability
If memory operations are paused during clock frequency changes to ensure stability, then reliability is improved, but productivity decreases due to suspended operations
Solution Approach 1:
The system performs preliminary actions to prepare for frequency changes, including flushing pending memory operations and coordinating with the memory controller before initiating the slew. This ensures that no operations are lost or corrupted during the transition, maintaining reliability while minimizing disruption.
Solution Approach 2:
The system maintains continuity of useful action by performing frequency changes during periods when memory bandwidth utilization is low or by rapidly completing changes during self-refresh modes. This minimizes the impact on productivity while ensuring stable transitions through coordinated pausing and resumption of operations.
4Productivity
If the clock frequency is rapidly changed to minimize downtime, then productivity is improved, but abrupt changes can cause system components to malfunction
Solution Approach 1:
The system dynamically adjusts the frequency change rate based on real-time system conditions. During critical operations, changes are performed more slowly to prevent malfunction, while during safe periods, changes are accelerated to minimize downtime, optimizing both productivity and reliability.
Solution Approach 2:
The system uses intermediate frequency steps as mediators between the initial and target frequencies. Each intermediate step allows system components to adapt gradually, preventing the harmful effects of abrupt changes while maintaining overall progress toward the frequency change goal, thus protecting components while improving change speed.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach minimizes downtime during clock frequency changes, ensuring continuous operation and power savings while accommodating PLL and DLL requirements, thus enhancing the reliability and efficiency of power management in memory subsystems.
Implementation Method 1
the system then iteratively changes the clock frequency to the new clock frequency. More specifically, the system starts an iteration by slewing the clock frequency toward the new clock frequency by an increment to reach an intermediate frequency
Data Source
AI summary
One embodiment of the present invention provides a system that facilitates changing a clock frequency in a memory system. During operation, the system receives a command to change the clock frequency to a new clock frequency. The system then iteratively changes the clock frequency to the new clock frequency. More specifically, the system starts an iteration by slewing the clock frequency toward the new clock frequency by an increment to reach an intermediate frequency without interfering with normal memory-system operation. Next, the system signals a memory controller to pause normal memory system operation by completing or cancelling all in-flight or outstanding memory system operations and not accepting additional memory operation requests. Upon receiving an acknowledgement from the memory controller that all in-flight or outstanding memory operations have completed or terminated, the system signals the memory controller to cause a delay-locked loop (DLL) inside the memory system to relock to the intermediate frequency. When the DLL relocks to the intermediate frequency, the system completes the iteration by resuming normal memory system operation.