Memory Clock Mode Switching for Signal-Integrity-Limited Arrays
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Solution Overview
Problem
The existing flash memory systems face performance limitations due to signal integrity issues such as crosstalk, signal skew, and simultaneous switching noise, as well as increased power consumption with higher system clock frequencies, which restrict the number of memory devices that can be connected in parallel and require additional chip enable signals and clock distribution, leading to increased costs.
Innovation Solution
A semiconductor device with a configurable input circuit that can operate in modes for receiving coincident or non-coincident clock and data edges, allowing for serial connection of memory devices in a ring topology configuration, enabling the use of either parallel or serial clock signals and reducing the need for extensive clock distribution.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple memory devices are connected in parallel to increase storage capacity, then the available storage capacity increases, but signal integrity is degraded by crosstalk, signal skew, and simultaneous switching noise
Solution Approach 1:
The patent segments the clock distribution into multiple separate clock lines, each serving a subset of memory devices. This segmentation reduces the number of devices sharing a single clock line, thereby reducing simultaneous switching noise and signal skew while still allowing multiple devices to be connected for increased capacity
Solution Approach 2:
The patent introduces clock buffer circuits as intermediary elements between the clock source and memory devices. These buffers act as mediators that drive individual clock lines to reduce loading effects and minimize signal degradation from crosstalk and skew, thereby maintaining signal integrity while supporting multiple devices
2Speed
If the system clock frequency is increased to improve operation speed, then the operation speed increases, but power consumption increases due to frequent charging and discharging of signal tracks
Solution Approach 1:
The patent employs periodic clock gating, where clock signals are selectively enabled or disabled to memory devices based on whether they are currently active or in standby mode. This periodic action allows the system to maintain high clock frequencies when needed while reducing average power consumption by eliminating unnecessary clock transitions during idle periods
Solution Approach 2:
The patent implements dynamic clock frequency adjustment, allowing different clock frequencies to be applied to different memory devices or different time periods based on system requirements. This dynamic approach enables high-speed operation when performance is needed while reducing power consumption during lower-demand operations
3Quantity of substance
If the number of memory devices connected in parallel increases, then the storage capacity increases, but more chip enable signals and clock distribution are required, increasing system complexity and cost
Solution Approach 1:
The patent merges multiple memory devices into bank groups that share common control signals including chip enable and clock lines. By organizing devices into banks with shared resources, the system can support a large number of devices while reducing the total number of control signals required, thereby lowering system complexity and cost
Data Source
AI summary
A clock mode configuration circuit for a memory device is described. A memory system includes any number of memory devices serially connected to each other, where each memory device receives a clock signal. The clock signal can be provided either in parallel to all the memory devices or serially from memory device to memory device through a common clock input. The clock mode configuration circuit in each memory device is set to a parallel mode for receiving the parallel clock signal, and to a serial mode for receiving a source synchronous clock signal from a prior memory device. Depending on the set operating mode, the data input circuits will be configured for the corresponding data signal format, and the corresponding clock input circuits will be either enabled or disabled. The parallel mode and the serial mode is set by sensing a voltage level of a reference voltage provided to each memory device.