Memory Module Clock Switching for Stable Surprise Clock Stops
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Solution Overview
Problem
Memory modules face data integrity and security issues due to sudden or unexpected clock stops, leading to circuit instability, data loss, and firmware state corruption, as they may have different perspectives on transaction status with the host processor, and existing solutions require lengthy reset sequences or introduce glitches in the clock distribution network.
Innovation Solution
A unique arrangement of circuit components including a clock detector circuit, a clock-smoothing circuit, and phase locked loops (PLLs) ensures a stable and continuous clock by seamlessly switching to an alternate reference clock source, such as an on-module crystal oscillator, maintaining steady phase and frequency without inducing glitches or period excursions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a sudden or unexpected clock stop is detected, then the memory module can prevent circuit instability and data loss, but the host and memory module may have different perspectives on transaction status leading to data integrity issues
Solution Approach 1:
The memory module performs preliminary actions by detecting clock stops and initiating alternate clock source switching before data corruption can occur. The system proactively monitors clock signals and prepares backup clock sources to maintain operation continuity, preventing the transaction status mismatch from developing into data integrity issues.
Solution Approach 2:
The system implements feedback mechanisms where the memory module continuously monitors the clock signal status and compares it with expected operation patterns. When a clock stop is detected, the feedback loop triggers automatic switching to alternate clock sources and initiates appropriate reset sequences, ensuring both host and memory module maintain consistent views of transaction status.
2Reliability
If a reset sequence is initiated after a surprise clock stop, then circuit stability can be restored, but the reset sequence takes many thousands of clock cycles causing delayed operation completion
Solution Approach 1:
The system performs preliminary preparation by maintaining alternate clock sources ready to activate immediately upon clock stop detection. Rather than waiting for a full reset sequence, the alternate clock source is pre-configured and can take over instantly, restoring circuit stability in a fraction of the time required for traditional reset procedures.
Solution Approach 2:
The system changes operational parameters by switching from the primary host clock to an alternate clock source (such as an on-module crystal oscillator). This parameter change allows the system to maintain stable operation without undergoing a lengthy reset sequence, as the alternate clock source is designed to immediately assume the clocking function with appropriate frequency and phase characteristics.
3Duration of action of stationary object
If an on-die ring oscillator is used as an alternate clock source, then clock continuity can be maintained, but the oscillator may be noisy and drift over time causing timing failures
Solution Approach 1:
The system uses an intermediary approach by selecting an on-module crystal oscillator as the alternate clock source. This crystal oscillator acts as a mediator between the host clock and the memory module's internal timing requirements, providing stable and accurate frequency reference that minimizes drift and noise while maintaining clock continuity during host clock failures.
Solution Approach 2:
The system changes the clock source parameter from an on-die ring oscillator to an on-module crystal oscillator. This parameter change improves timing accuracy by selecting a clock source with inherently lower noise and drift characteristics, while the crystal oscillator's stability ensures reliable operation throughout the clock stop event and subsequent recovery period.
4Reliability
If a PLL switches reference clocks seamlessly, then clock stability can be maintained, but the system requires complex circuit components including clock detector circuit and clock-smoothing circuit
Solution Approach 1:
The system segments the clock management function into distinct modular components: a clock detector circuit for monitoring host clock status, a multiplexer for clock source selection, a PLL for frequency synthesis and phase alignment, and a clock-smoothing circuit for glitch reduction. This segmentation allows each component to perform its specific function efficiently, maintaining clock stability while organizing complexity into manageable, independent modules.
Solution Approach 2:
The system introduces intermediary components to manage the complexity of clock switching. The multiplexer acts as an intermediary for clean clock source selection, the PLL serves as an intermediary for frequency translation and phase synchronization, and the clock-smoothing circuit acts as an intermediary to filter out switching transients. These intermediary elements maintain clock stability while providing structured interfaces between different clock management functions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Guarantees timely completion of operations, maintains data integrity, reduces the need for lengthy reset sequences, and minimizes the expense and area required for hold-up capacitors, ensuring stable clocking both before and after a surprise clock stop event.
Implementation Method 1
a phase locked loop (PLL) to receive an output of the first circuitry as a reference clock to the PLL
Data Source
AI summary
Both before and after a surprise clock stop, the apparatus and method of various embodiments supplies a stable and continuous clock to a memory module with a unique arrangement of circuit components, including a clock detector circuit, a clock-smoothing circuit, and one or more PLLs. Upon detection of a stopped host clock, a first PLL seamlessly switches to an alternate reference clock from an on-board crystal oscillator. A clock smoothing circuit allows the first PLL to maintain a steady phase and frequency without inducing glitches or period excursions greater than the natural jitter of the locked PLL; one or more optional downstream PLLs may drive additional clock domains.