Memory Controller Clock Synchronization via Enable Signal
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Solution Overview
Problem
Existing memory systems face challenges in synchronizing system clock signals and data clock signals of different frequencies, which can lead to malfunctions in semiconductor apparatuses.
Innovation Solution
A memory system comprising a memory controller and memory devices, where the memory controller provides system clock signals, data clock signals, chip selection signals, and a data clock enable signal to facilitate synchronization between the system clock and data clock signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If system clock signal and data clock signal of different frequencies are used to improve data communication speed, then data communication speed is improved, but clock synchronization becomes difficult and may lead to malfunction
Solution Approach 1:
A data clock enable signal is introduced as an intermediary to coordinate between the system clock signal and data clock signal. This enable signal is provided after a memory access is performed, allowing the memory device to synchronize its internal timing with the controller's timing requirements, thus resolving the synchronization difficulty between different frequency clocks
Solution Approach 2:
The data clock enable signal is provided in advance after a memory access is performed, before actual data transmission occurs. This preliminary action allows the memory device to prepare its internal timing circuits and synchronize with the controller's timing, ensuring reliable operation when high-speed data clock is activated
2Reliability
If traditional clock synchronization method is used, then clock synchronization can be achieved, but static section and half-rate section are required which increases synchronization time
Solution Approach 1:
The invention extracts and eliminates the static section and half-rate section from the traditional clock synchronization method. By using the data clock enable signal to directly control the activation of the data clock, the system achieves clock synchronization without requiring these intermediate timing sections, thereby reducing synchronization time while maintaining reliability
Data Source
AI summary
A memory system includes a memory controller and a memory device. The memory controller accesses the memory device by providing a system clock signal, a data clock signal, and a chip selection signal and provides a data clock enable signal to the memory device after the access to the memory device. The memory device communicates with the memory controller based on the system clock signal, the data clock signal, and the data clock enable signal.