Memory Apparatus Clock Synchronization via Preamble Data
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Solution Overview
Problem
Existing memory devices face challenges in synchronizing the sampling clock signal of a host device with data transmission, which is crucial for proper data access and retrieval in non-volatile memory systems.
Innovation Solution
A memory apparatus and method that utilize a first command sub-period, a dummy sub-period, and a data transmission sub-period to synchronize external and internal clock signals by using a control unit to provide a control signal and preamble data, allowing the host device to determine alignment and adjust the external clock signal accordingly.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the host device uses an external clock signal to sample data, then the data transmission can be performed, but the external clock signal may not be aligned with the internal clock signal of the slave device, causing sampling errors
Solution Approach 1:
The patent applies preliminary action by transmitting preamble data before the actual data transmission. The host device samples this preamble data using its external clock signal to determine the alignment relationship with the slave device's internal clock signal. This preliminary sampling allows the host to adjust its external clock signal phase or frequency before receiving the actual data, ensuring accurate sampling without requiring complex real-time synchronization mechanisms.
Solution Approach 2:
The patent implements feedback by using the sampled preamble data to determine clock alignment and adjusting the external clock signal accordingly. The host device compares the timing of received preamble data with expected timing based on the internal clock signal, detects any misalignment, and feeds this information back to adjust the external clock signal's phase or frequency, creating a closed-loop synchronization system.
2Productivity
If the memory device transmits data immediately after receiving a command, then the data transmission speed is improved, but the host device may not be ready to sample the data, causing timing mismatches
Solution Approach 1:
The patent uses preliminary action by inserting a dummy sub-period between the command sub-period and data transmission sub-period. During this dummy sub-period, the slave device transmits preamble data that allows the host device to prepare its sampling timing. This preliminary data transmission enables the host to synchronize its external clock signal before the actual data becomes available, eliminating timing mismatches without significantly delaying the overall data transmission.
3Measurement precision
If the host device adjusts its external clock signal to match the internal clock signal, then timing synchronization is achieved, but the complexity of the synchronization mechanism increases
Solution Approach 1:
The patent applies self-service by enabling the host device to autonomously determine its own clock alignment using the transmitted preamble data. The host device independently samples the preamble data, compares it with its internal timing reference, determines the alignment relationship with the slave device's internal clock signal, and adjusts its external clock signal without requiring complex external synchronization hardware or complex control logic in the slave device.
Data Source
AI summary
A memory apparatus includes a host device and a slave device. The host device stores verification data. The slave device includes a memory unit, a control unit, and a logic unit. The control unit drives the memory unit to provide storage data in a data transmission sub-period, and further provides a control signal, indicating the first verification data, in a dummy sub-period. The logic unit provides first preamble data, indicating substantially a same data value as the verification data, in the dummy sub-period in response to the first control signal. The preamble data and the storage data are transmitted according to an internal clock signal. The host device samples the first preamble data according to an external clock signal, and determines whether the external and the internal clock signals are synchronized by comparing the first preamble data and the first verification data.