Semiconductor Memory Clock Synchronization Without Strobe Signals
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Solution Overview
Problem
Semiconductor memory devices face challenges in maintaining stable operations due to skew between clock and data signals, and external noise interference, which existing clock data recovery methods fail to adequately address by not considering the role of data strobe signals.
Innovation Solution
A semiconductor memory device that delays data signals using control signals to generate internal clock signals, incorporating a clock period reflector, data-clock converter, and synchronization output unit to synchronize input data signals, thereby securing sufficient margin between clock and data signals without requiring separate strobe signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If clock data recovery method is used to eliminate external strobe signals, then device complexity is reduced, but synchronization stability deteriorates due to skew between clock and data signals
Solution Approach 1:
The patent introduces a delay circuit as an intermediary component that mediates between the clock signal and data signal. This delay circuit adjusts the timing of one signal relative to the other, acting as a buffer to compensate for skew and achieve proper synchronization without requiring external strobe signals.
Solution Approach 2:
The patent changes the timing parameter of the clock or data signal by introducing a controllable delay. By adjusting the delay amount, the system optimizes the synchronization between clock and data signals, maintaining reliable operation while eliminating external strobe requirements.
2Reliability
If delay circuit is introduced to synchronize clock and data signals, then synchronization stability is improved, but device complexity increases due to additional circuit components
Solution Approach 1:
The delay circuit is designed to perform multiple functions: it not only delays signals for synchronization but also provides noise filtering and timing adjustment capabilities. This multi-functionality reduces the need for separate dedicated circuits for each function, thereby limiting the increase in overall device complexity.
3Reliability
If delay circuit is used to secure synchronization margin, then synchronization stability is improved, but noise susceptibility increases due to delay configuration
Solution Approach 1:
The delay circuit is designed with inherent noise immunity features that cushion against noise effects before they can significantly impact the synchronized signals. The delay configuration is optimized to provide sufficient timing margin while minimizing noise accumulation during the delay period.
Data Source
AI summary
A semiconductor memory device includes a clock period reflector configured to reflect time corresponding to period information of an internal clock signal to an input data signal, a data-clock converter configured to generate a synchronization clock signal having phases corresponding to an output signal of the clock period reflector, and a synchronization output unit configured to synchronize and output the input data signal in response to the synchronization clock signal.