Memory Control Clock Timing Adjustment Circuit
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Solution Overview
Problem
The challenge lies in adjusting the timing of data access between a signal processing circuit and an external memory, which becomes increasingly difficult due to fluctuations in circuit characteristics and external factors, making it hard to maintain synchronization as data processing speeds increase.
Innovation Solution
A signal processing circuit with a timing adjustment section that changes the delay time of the memory control clock, allowing for automatic selection of a suitable delay time based on comparisons between written and read data values, ensuring optimal access timing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If data processing speed is increased, then productivity is improved, but timing adjustment difficulty increases
Solution Approach 1:
The system performs automatic timing adjustment by itself without external intervention. The timing adjustment section automatically modifies the memory control clock timing based on detection results from the read comparison section, enabling the system to self-correct timing issues that arise at higher data processing speeds
Solution Approach 2:
A feedback mechanism is established where the read comparison section detects whether read data matches written data, and this detection result is fed back to control the timing adjustment section. This closed-loop feedback enables automatic timing optimization as data processing speed increases
2Adaptability or versatility
If manual timing adjustment is performed, then adaptability is improved, but ease of operation deteriorates
Solution Approach 1:
The system automatically adjusts timing parameters based on detection results without requiring manual intervention. The timing adjustment section modifies the memory control clock timing autonomously based on feedback from the read comparison section, making the system adaptable while easy to operate
Solution Approach 2:
The read comparison section provides feedback on data integrity, which automatically controls the timing adjustment section to modify timing parameters. This feedback loop enables the system to adapt to different operating conditions without manual timing adjustment operations
Data Source
AI summary
A delay time of a reference clock CLK is changed to generate a memory control clock CLKd, a data value output from a write data generating section is written in a memory based on the memory control clock CLKd, while successively changing the delay time of the memory control clock CLKd with respect to the reference clock CLK, the data value written in the memory is read, and the delay time suitable for access to the memory is selected from the delay time of the memory control clock CLKd with respect to the reference clock CLK based on a comparison result of the data values.