Memory System Clock Signal Adjustment for TLC Write Power
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Solution Overview
Problem
Memory systems face limitations in achieving maximum data transfer rates due to excessive power consumption, particularly during write operations for high-density memory cells like TLCs, which leads to throttled data transfer rates to conserve power, thereby impacting performance.
Innovation Solution
Modifying the clock signal, such as halving the number of clock cycles or adjusting its periodicity, to reduce power consumption during data transfer operations, allowing for higher data transfer rates without increasing latency, especially during TLC write operations by exiting high performance modes or managing media operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the memory system operates at maximum data transfer rates, then productivity is improved, but power consumption increases excessively
Solution Approach 1:
The patent implements dynamic clock rate adjustment where the clock signal frequency is modified based on the type of memory operation being performed. During TLC write operations, the clock rate is reduced from a first rate to a second rate, creating a dynamic adaptation that lowers power consumption during high-energy operations while maintaining higher rates for other operations.
Solution Approach 2:
The patent changes the clock signal parameter (frequency/rate) depending on the operation type. By switching between different clock rates (first clock rate for normal operations, second clock rate for TLC writes), the system optimizes the balance between productivity and power consumption for different operational contexts.
2Use of energy by moving object
If the clock rate is reduced to conserve power, then power consumption is decreased, but data transfer rate is throttled
Solution Approach 1:
The patent applies partial clock rate reduction only during specific high-power operations (TLC writes) rather than uniformly reducing the clock rate for all operations. This selective approach reduces power consumption during the most energy-intensive operations while maintaining higher data transfer rates for other operations that don't require maximum power.
Solution Approach 2:
The system dynamically adjusts the clock rate based on operational needs, switching between first and second clock rates depending on whether TLC write operations are being performed. This dynamic adjustment allows the system to optimize power consumption during specific operations without permanently throttling the overall data transfer capability.
3Productivity
If high performance mode is used for faster data transfer, then productivity is improved, but power consumption exceeds thresholds
Solution Approach 1:
The patent implements a dynamic performance management system that switches between high performance mode (first clock rate) and power-efficient mode (second clock rate) based on the operation type. During TLC writes, the system transitions to the lower clock rate to stay within power thresholds, while maintaining high performance mode for operations that can operate within power constraints.
Solution Approach 2:
The system changes the clock rate parameter conditionally based on the operation being performed and power threshold status. By monitoring power consumption and adjusting the clock rate accordingly, the system maintains compliance with power thresholds while maximizing productivity when possible.
Data Source
AI summary
Methods, systems, and devices for managing power consumption associated with communicating data in a memory system are described. A memory system may selectively reduce a periodicity of a clock signal for one or more types of write operations, which may improve power consumption associated with data transfer rates during the one or more types of write operations. For example, the memory system may modify the clock signal for triple-level cell (TLC) write operations. The memory system reduce a periodicity of the clock signal to improve performance for TLC write operations by trading communication speed for internal array performance. Additionally, or alternatively, some media management operations performed by the memory system that involve transferring data to higher-density memory cells may trigger the memory system to modify the clock signal.