Memory Clock Tree Voltage Control for Fast Mode Switching
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Solution Overview
Problem
The significant voltage drop of the power supply voltage in the clock tree during power saving mode can cause data access errors when switching to normal mode due to the time required for the voltage to reach the expected level, impacting the performance of memory apparatus.
Innovation Solution
A memory apparatus with a synchronous circuit, clock tree, and memory controller that adjusts the frequency of the clock signal based on the operating mode, using a delay locked loop circuit, frequency divider, and multiplexer to output either the clock signal or a frequency division signal to the clock tree, reducing power consumption and stabilizing the voltage drop.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If the operating voltage is lowered in power saving mode, then energy consumption is reduced, but the voltage takes too long to rise to the expected level when switching to normal mode
Solution Approach 1:
The patent applies preliminary action by pre-charging the power supply voltage of the clock tree to an intermediate level (e.g., 0.7V) before switching from power saving mode to normal mode. This preliminary voltage adjustment reduces the time required for the voltage to reach the maximum operating level (e.g., 1.2V) when data access is needed, thereby resolving the contradiction between energy saving and fast voltage rise time.
2Loss of energy
If the power supply voltage is significantly dropped in power saving mode, then energy is saved, but the system clock fails to reach expected voltage in predetermined time
Solution Approach 1:
The patent uses preliminary action by adjusting the power supply voltage to an intermediate level before mode switching, ensuring that when transitioning to normal mode, the voltage can quickly reach the required level for reliable data access, thus maintaining system reliability while still achieving energy savings during idle periods.
Solution Approach 2:
The patent applies dynamics by making the power supply voltage adjustable and time-dependent. The voltage is dynamically changed based on the operational state: lowered to an intermediate level during power saving mode and quickly raised to maximum level during normal mode, allowing the system to adapt to different operational requirements and resolve the contradiction between energy saving and reliability.
3Use of energy by stationary object
If the clock signal frequency is reduced in power saving mode, then power consumption is reduced, but the voltage stabilization time increases when switching to normal mode
Solution Approach 1:
The patent applies preliminary action by pre-adjusting the power supply voltage to an intermediate level before switching from power saving mode to normal mode. This preliminary voltage adjustment ensures that when the clock signal frequency is increased, the voltage stabilizes faster, thereby resolving the contradiction between reduced power consumption and reduced voltage stabilization time.
Data Source
AI summary
A memory apparatus and a voltage control method of the memory apparatus are provided. The memory apparatus of the invention includes a synchronous circuit, a clock tree and a memory controller. The synchronous circuit receives a reference clock and generating a clock signal. The clock tree is coupled to an output end of the multiplexer and assigns the clock signal to a plurality of signal paths. The memory controller is coupled to the synchronous circuit and controls the synchronous circuit to adjust a frequency of the clock signal according to an operating mode of the memory apparatus.