Memory Cloud Resource Sharing for Heterogeneous Processors
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Solution Overview
Problem
Current semiconductor technologies lack an optimized memory cluster configuration for large-capacity multicasting, and existing methods for increasing DRAM capacity are limited by cost, scalability, and dependence on memory suppliers, particularly in deep learning applications that require high memory bandwidth.
Innovation Solution
A memory control interoperation method and system that configures a memory cloud capable of sharing memory resources between heterogeneous processors, using a memory resource sharing system with a memory bus for direct data transmission between memory subsystems, enabling independent scalability of processors and memory capacity and minimizing access delay.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If individual DRAM capacity is increased or DIMM is expanded to meet large capacity requirements, then memory capacity is improved, but cost increases and scalability is limited due to dependence on memory suppliers
Solution Approach 1:
The patent divides the memory system into multiple independent memory modules (first memory, second memory, third memory, fourth memory) that can be independently configured and managed. Each memory module operates as a separate entity with its own memory controller, allowing the system to scale by adding or removing individual modules without being constrained by single-module capacity limits or supplier dependencies.
Solution Approach 2:
The memory cloud system creates a universal memory pool that can serve multiple heterogeneous processors (CPU, GPU, NPU, etc.) simultaneously. The memory resources are abstracted into a unified pool that can be dynamically allocated to different processor types and workloads, making the system adaptable to various computing scenarios without requiring dedicated memory for each processor type.
2Adaptability or versatility
If memory resources are shared between heterogeneous processors through a memory cloud, then interoperability and scalability are improved, but system complexity increases due to multiple memory subsystems and coordination requirements
Solution Approach 1:
The patent introduces a memory cloud controller as an intermediary that manages communication and coordination between multiple memory subsystems and heterogeneous processors. This mediator handles memory allocation, address translation, and data routing, abstracting the complexity from individual processors while enabling seamless interoperability across different processor types and memory modules.
Solution Approach 2:
The memory system employs a nested hierarchical structure where individual memory modules are nested within memory pools, which are in turn nested within the overall memory cloud system. This nested organization allows each level to manage its own resources independently while contributing to the larger system, reducing the complexity burden on any single component.
3Speed
If a memory cloud network is configured with multiple processors and memory modules, then data transmission speed is improved, but access delay may increase due to network routing and coordination overhead
Solution Approach 1:
The memory cloud system performs preliminary actions by pre-allocating memory resources and establishing data pathways before actual data access occurs. Memory buffers are pre-configured and data is pre-positioned in optimal locations, reducing the time required for actual data retrieval and transmission while maintaining high-speed connectivity across the memory cloud network.
Data Source
AI summary
Provided is a memory resource sharing system including a first memory, a first memory subsystem configured to identify and distribute resources of the first memory and to control data transmission of the first memory, and a first processor unit including a first processor connected to the first memory subsystem, a second memory, a second memory subsystem configured to identify and distribute resources of the second memory and to control data transmission of the second memory, and a second processor unit including a second processor connected to the second memory subsystem, wherein the first memory subsystem and the second memory subsystem are communicatively connected to each other through a memory bus.