Memory Code Rate Adjustment Based on Endurance State
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Solution Overview
Problem
Memory sub-systems face inefficiencies in managing code rate based on memory endurance state metrics, leading to suboptimal endurance and capacity utilization, particularly due to over-provisioning requirements that are not cost-effective and do not adapt to the device's lifecycle stages.
Innovation Solution
The memory sub-system adjusts the code rate by determining a target value based on a chosen memory endurance state metric, such as program erase cycles or raw bit error rate, using a look-up table or sample data, to dynamically allocate resources between user data and error correction data, thereby increasing memory endurance and extending the useful life of the device.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a fixed code rate is used throughout the memory device lifetime, then the memory sub-system can maintain consistent error correction capability, but it leads to suboptimal endurance and capacity utilization due to over-provisioning requirements
Solution Approach 1:
The patent implements dynamic code rate adjustment based on the memory device's endurance state. The controller monitors program-erase cycle counts and other wear metrics, then adapts the code rate accordingly. When the device is new, a lower code rate (less error correction) is used to maximize capacity. As the device ages and endurance decreases, the code rate increases to maintain reliability, eliminating the need for excessive over-provisioning and improving overall capacity utilization throughout the device lifetime.
Solution Approach 2:
The patent changes the code rate parameter based on measured endurance state metrics. By monitoring program-erase cycle counts and adjusting the code rate parameter dynamically, the system optimizes the balance between error correction capability and capacity utilization. This parameter adaptation allows the memory sub-system to maintain appropriate reliability while maximizing usable capacity at different stages of the device lifecycle.
2Reliability
If over-provisioning is increased to extend memory device endurance, then reliability is improved, but costs increase without proportional benefits and capacity is wasted
Solution Approach 1:
The system dynamically adjusts the proportion of capacity allocated to error correction versus user data based on the device's actual wear state. Instead of statically over-provisioning with a fixed large percentage reserved for error correction, the system starts with minimal over-provisioning when the device is new and gradually increases error correction allocation as the device approaches endurance limits. This dynamic reallocation maximizes usable capacity while maintaining adequate reliability throughout the device lifecycle.
3Productivity
If a lower code rate is used to maximize capacity, then more user data can be stored, but error correction capability decreases and reliability is compromised
Solution Approach 1:
The patent implements a dynamic code rate adjustment mechanism that adapts to the memory device's endurance state. When the device is new with high remaining endurance, a lower code rate is applied to maximize user capacity. As the device accumulates program-erase cycles and endurance decreases, the controller automatically increases the code rate to strengthen error correction capability. This dynamic approach ensures that capacity is maximized when possible while reliability is maintained when needed, eliminating the need to choose a fixed suboptimal code rate.
Data Source
AI summary
A method includes determining, by a processing device, a value of a memory endurance state metric associated with a segment of a memory device in a memory sub-system; determining a target value of a code rate based on the value of the memory endurance state metric, and adjusting the code rate of the memory device according to the target value, wherein the code rate reflects a ratio of a number of memory units designated for storing host-originated data to a total number of memory units designated for storing the host-originated data and error correction metadata.