Memory Error Correction Using Adjustable Code-Rate and Strong LLR
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Solution Overview
Problem
Existing error correction techniques for memory cells, such as Reed-Solomon and BCH codes, have limited error correction capabilities as the number of errors increases, leading to data integrity issues due to noise and cell damage over time, particularly in NAND flash memory, which requires flexible and resource-efficient solutions to maintain data accuracy.
Innovation Solution
An integrated circuit device with an encoder and decoder configured from a single parity check matrix, allowing for virtual adjustments in code-rate and log-likelihood ratio settings to adapt to changing error rates, enabling flexible error correction across various memory cell types and use cases without the need for dedicated hardware for each scenario.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If Reed-Solomon and BCH codes are used for error correction, then data integrity is maintained, but error correction capability is limited when the number of errors increases
Solution Approach 1:
The patent implements dynamic error correction by adjusting the code-rate based on the actual error rate observed in the data. The system monitors the number of errors and dynamically selects appropriate error correction codes from a set of available codes with different correction capabilities, allowing the error correction strength to adapt to the actual error conditions rather than using a fixed code-rate
Solution Approach 2:
The system changes the parameter of code-rate to optimize error correction. By selecting from multiple error correction codes with different code-rates (e.g., different redundancy levels), the system can adjust the error correction capability to match the observed error rate, improving both data integrity and resource efficiency
2Reliability
If dedicated hardware is designed for specific error correcting solutions, then error correction performance is optimized, but design flexibility is limited
Solution Approach 1:
The patent implements a universal error correction architecture that can handle multiple types of error correction codes (Reed-Solomon, BCH, and other algebraic codes) within a single hardware platform. The system selects and configures the appropriate code based on the observed error rate, allowing one hardware design to serve multiple error correction needs without requiring separate dedicated hardware for each code type
Solution Approach 2:
The error correction system dynamically adapts its configuration based on observed error rates. The controller monitors errors and dynamically selects from a set of pre-configured error correction codes with different capabilities, allowing the same hardware to optimize performance for different error conditions without requiring physical reconfiguration or multiple dedicated hardware paths
3Adaptability or versatility
If new error correction solutions are implemented for each use case, then specific design criteria are met, but resources must be expended for multiple implementations
Solution Approach 1:
The patent creates a unified error correction platform that can accommodate different use cases (minimum memory access times, minimum chip space, different error rates) through a single implementation. The system selects from multiple error correction codes with different characteristics (code-rates, correction capabilities) based on the observed error rate and system requirements, eliminating the need for separate hardware implementations for different use cases
Data Source
AI summary
Apparatuses and methods for correcting errors in data read from memory cells of an integrated circuit device includes an encoder. The encoder is configured from a single parity check matrix and the encoder is configured to be virtually adjustable by setting a number of bits in the encoder to zero. A decoder is configured from the single parity check matrix and the decoder is configured to be virtually adjustable by setting a log-likelihood ratio (LLR) for a number of bits in the decoder to a strong value. A code-rate that the encoder and decoder uses can be changed by adjusting the number of bits in the encoder that are set to zero and the number of bits in the decoder that are set to the strong LLR value.