Memory Codeword Partitioning for Low-Latency Error Correction
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Solution Overview
Problem
Existing error detection and correction schemes in memory devices negatively impact system performance and increase manufacturing costs due to the need for large amounts of logic circuitry and increased latencies, especially when applied to larger data segments.
Innovation Solution
Implementing error detection and correction operations for sub-codewords within memory devices without accessing the entire codeword, utilizing cyclic redundancy check (CRC) bits and partitioning codewords into sub-codewords to reduce overhead and improve performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If error detection and correction schemes are implemented for entire codewords in memory devices, then reliability is improved, but device complexity and manufacturing costs increase due to large amounts of logic circuitry required
Solution Approach 1:
The patent divides a codeword into multiple sub-codewords, each with its own error detection code. This segmentation allows error detection to be performed on individual sub-codewords rather than requiring circuitry for the entire codeword, thereby reducing the amount of logic circuitry needed while maintaining reliability for the accessed portion.
Solution Approach 2:
The patent extracts and removes selected sub-codewords from the larger codeword structure for independent error detection. By taking out only the necessary sub-codewords that need error checking, the system avoids implementing error detection circuitry for the entire codeword, reducing device complexity while preserving reliability for the extracted portions.
2Reliability
If error detection and correction schemes are implemented for entire codewords, then reliability is improved, but system performance deteriorates due to increased latencies
Solution Approach 1:
By segmenting the codeword into sub-codewords with individual error detection codes, the system can perform error detection on smaller, independently accessible units. This reduces the time required for error detection operations compared to processing the entire codeword, thereby improving system performance while maintaining reliability.
Solution Approach 2:
The patent applies error detection only to the specific sub-codewords that are accessed or need verification, rather than performing error detection on the entire codeword. This partial action approach reduces the time and resources required for error detection while maintaining sufficient reliability for the accessed data portions.
3Ease of manufacture
If error detection and correction are applied to larger data segments to reduce parity bits, then manufacturing costs decrease, but device complexity increases due to larger logic circuitry requirements
Solution Approach 1:
The patent segments the data into sub-codewords with individual error detection codes, creating a middle ground between processing small units and large segments. This segmentation reduces the total number of parity bits needed compared to small-unit encoding while avoiding the excessive logic circuitry requirements of processing entire large codewords, thereby improving ease of manufacture without significantly increasing device complexity.
Data Source
AI summary
Example embodiments described herein may relate error detection and correction on a portion of a codeword in a memory device.