Memory Codeword Addressing Using XOR Offsets for Error Correction
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Solution Overview
Problem
Existing memory technologies face challenges in error correction due to mechanisms like read disturb and current leakage, leading to erroneous data states in resistance variable memory cells, which are not effectively addressed by complex address offset mechanisms that reduce memory throughput.
Innovation Solution
The implementation of an XOR-based address offset mechanism that can be performed on any bits of the address, rather than just the most significant bits, to ensure different portions of codewords are programmed at different electrical distances from row and column decoders, enhancing memory throughput and error correction efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If complex address offset mechanisms are used to correct errors in resistance variable memory cells, then error correction effectiveness is improved, but memory throughput deteriorates
Solution Approach 1:
The patent changes the parameter of address offset calculation from complex multi-step arithmetic operations to simple XOR bitwise operations. This parameter change maintains error correction effectiveness by still distributing codeword portions across different electrical distances, while dramatically improving memory throughput by reducing computational complexity and operation time.
Solution Approach 2:
The patent substitutes complex arithmetic mechanical operations (addition, multiplication, modulo) with simpler logical bitwise XOR operations. This substitution reduces the computational overhead and time required for address offset calculation, thereby improving memory throughput while maintaining the essential function of distributing error correction operations across different electrical distances.
2Device complexity
If address offset operations are performed on only the most significant bits, then device complexity is reduced, but error correction uniformity deteriorates
Solution Approach 1:
The patent applies the XOR operation universally across all bits of the address (or selectable bit positions), making the address offset mechanism equally simple while achieving uniform error correction distribution. This universal application ensures that codeword portions are evenly distributed across different electrical distances throughout the memory array, improving error correction uniformity without increasing device complexity.
3Speed
If read operations are performed frequently on resistance variable memory cells, then data access speed is improved, but read disturb effects increase causing more erroneous data states
Solution Approach 1:
The patent performs error correction operations (writing correction codewords to memory cells) in advance, before erroneous data states accumulate from repeated read operations. By proactively correcting errors using the XOR-based address offset mechanism, the system maintains data state accuracy and prevents read disturb effects from degrading reliability, while preserving fast data access speeds.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach simplifies and accelerates the address offset process, improving the effectiveness and uniformity of error correction operations, thereby increasing memory throughput and reliability.
Implementation Method 1
resistance variable memory cells that can store data based on the resistance state of a storage element (e.g., a memory element having a variable resistance)
Implementation Method 2
A state of a resistance variable memory cell can be determined by sensing current through the cell responsive to an applied interrogation voltage. The sensed current, which varies based on the resistance level of the cell, can indicate the state of the cell.
Data Source
AI summary
The present disclosure includes apparatuses, methods, and systems for programming codewords for error correction operations to memory. An embodiment includes a memory having a plurality of groups of memory cells, wherein each respective one of the plurality of groups includes a plurality of sub-groups of memory cells, and circuitry configured to program a portion of a codeword for an error correction operation to one of the plurality of groups of memory cells by determining an address in that group of memory cells by performing an XOR operation on an address of one of the plurality of sub-groups of that group of memory cells, and programming the portion of the codeword to the determined address.