Memory Coherence in Multi-Computer Systems via Selective Update

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Solution Overview

Problem

Existing systems for simultaneously operating multiple computers interconnected via a communications network face issues with memory coherence and performance due to stale data and delays in updating memory locations, particularly when one computer fails, leading to potential system failure.

Innovation Solution

A method and system that categorize memory locations into accessible and non-accessible categories, detect failures, and modify the reachability category to prevent updates to failed computers, ensuring memory coherence and system resilience.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If memory locations are replicated across multiple computers to enable simultaneous operation, then computing speed and productivity are improved, but system reliability deteriorates when one computer fails due to stale data and update delays

Engineering Contradiction:
Improvecomputing speedVSAvoidsystem reliability
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent segments memory locations into two distinct categories: first category memory locations that are replicated across multiple computers and require updating, and second category memory locations that are local to individual computers and do not require updating. This segmentation allows the system to selectively manage updates only where necessary, improving reliability by avoiding futile update attempts to failed computers while maintaining the productivity benefits of replication for accessible memory locations.

Inventive Principle:
Principle #1Segmentation

2Stability of the object's composition

If all memory locations are updated across all computers to maintain coherence, then memory coherence is improved, but network traffic and system complexity increase unnecessarily

Engineering Contradiction:
Improvememory coherenceVSAvoidupdate management complexity
Core Design Contradiction:
Stability of the object's compositionVSDevice complexity

Solution Approach 1:

The patent applies local quality by treating different memory locations differently based on their accessibility and update requirements. First category memory locations (replicated and accessible by multiple computers) require updating to maintain coherence, while second category memory locations (local to single computer) do not require updating. This differentiated approach maintains memory coherence where needed without unnecessarily increasing network traffic or update management complexity for local-only memory locations.

Inventive Principle:
Principle #3Local quality

3Stability of the object's composition

If the system attempts to update all memory locations including failed computers, then memory coherence is maintained, but network bandwidth and time are wasted on unsuccessful updates

Engineering Contradiction:
Improvememory coherenceVSAvoidupdate time
Core Design Contradiction:
Stability of the object's compositionVSLoss of time

Solution Approach 1:

The patent implements preliminary action by detecting computer failures before attempting updates. The failure detection means identifies when a computer has failed, and the reachability modifier preemptively removes the failed computer from the first category memory location reachability list. This preliminary detection and exclusion action prevents wasted network bandwidth and time on unsuccessful update attempts to failed computers while ensuring memory coherence is maintained for accessible memory locations through successful updates.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS7849369B2Failure resistant multiple computer system and method
Publication Date: 2010.12.07 WARATEK LTD
  • US7849369B2 patent drawing
  • US7849369B2 patent drawing
  • US7849369B2 patent drawing

AI summary

The updating of only some memory locations in a multiple computer environment in which at least one applications program (50) executes simultaneously on a plurality of computers M1, M2 . . . Mn each of which has a local memory, is disclosed. Memory locations (A, B, D, E, X) in said local memory are categorized into two groups. The first group of memory locations (X1, X2, . . . Xn, A1, A2, . . . An) are each present in other computers. The second group of memory locations (B, E) are each present only in the computer having the local memory including the memory location. Changes to the contents of memory locations in the first group only are transmitted to all other computers. A computer failure detection mechanism is disclosed to prevent updating of any first group memory locations of any failed computer.