Memory Coherency Manager Circuit Shared State Data Routing
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Solution Overview
Problem
In processing systems with multiple processor cores, existing memory coherency manager circuits often rely on primary shared memory for memory transaction requests, leading to increased latency and reduced performance when processor cores store memory lines in a shared state.
Innovation Solution
The proposed solution involves a memory coherency manager circuit that detects memory lines stored in a shared state across processor cores and communicates data from the processor core holding the memory line in a shared state to the requesting processor core, thereby reducing the need for primary shared memory access.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the memory coherency manager circuit relies on primary shared memory for servicing memory transaction requests, then data consistency is ensured, but latency increases and performance decreases
Solution Approach 1:
The patent introduces an intermediary mechanism (the shared state detection and data communication path between processor cores) that mediates between the memory coherency manager circuit and the primary shared memory. When data is available in shared state across processor cores, the system can service requests through this intermediary path rather than directly accessing primary memory, thus reducing latency while maintaining data consistency through the coherency management framework.
Solution Approach 2:
The system performs preliminary action by maintaining data in shared state across processor cores before actual memory transaction requests occur. This pre-positioning of data in accessible locations (processor core states) rather than relying solely on primary memory ensures that when requests arrive, the data is already prepared and available for rapid access, reducing the time penalty associated with primary memory access.
2Reliability
If the memory coherency manager circuit accesses primary shared memory for all memory transaction requests, then complete data availability is ensured, but system performance is reduced
Solution Approach 1:
The patent applies local quality by differentiating the data access path based on the local state of data in processor cores. Instead of treating all memory access requests uniformly (all going to primary memory), the system identifies requests where data exists in shared state locally and routes them through a faster local path, while still ensuring data availability through the coherency framework. This localized optimization improves performance without sacrificing reliability.
Solution Approach 2:
The memory access system is segmented into multiple paths: one path for data available in shared state (faster) and another path for data requiring primary memory access (slower but ensuring availability). This segmentation allows the system to optimize performance for common cases (shared state data) while maintaining reliability for all cases through the alternative path, thereby improving overall system performance without compromising data availability.
3Device complexity
If the memory coherency manager circuit services all requests through primary memory, then system complexity is minimized, but latency and performance degradation occur
Solution Approach 1:
The patent enables processor cores to self-service memory transaction requests by directly providing data to requesting cores when the data exists in shared state. This self-service mechanism eliminates the need for all requests to traverse the full path through the memory coherency manager circuit and primary memory, reducing latency. The added complexity is localized to the shared state detection and routing logic, while the bulk of operations benefit from the simplified, faster direct path.
Data Source
AI summary
A system and method service memory transaction requests by receiving a memory transaction request for a first memory line from a first processor core of processor cores of a processing system. A second processor core of the processor cores is determined to include the first memory line in a shared state. Data of the first memory line is communicated from the second processor core to the first processor core based on determining that the second processor core comprises the first memory line in a shared state.