Memory Controller Color Pipelines for Flexible High-Speed Scheduling
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Solution Overview
Problem
Conventional memory interface circuitry on programmable integrated circuits either lacks scheduling efficiency for memory bandwidth utilization or is limited in flexibility when scaling across different memory protocols and topologies, with hardened solutions offering high performance but limited scalability and soft solutions providing flexibility but poor performance.
Innovation Solution
The memory controller architecture is partitioned into memory protocol agnostic blocks, protocol dependent blocks, and user dependent blocks, with multiple color pipelines operating in parallel to process memory access requests, and a rate matching circuit for clock domain crossing, allowing for flexible configuration and improved scheduling efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If hardened/fixed application-specific memory interface solutions are used, then operating frequency and performance are improved, but adaptability to different memory protocols and topologies deteriorates
Solution Approach 1:
The memory interface is divided into multiple independent color pipelines (e.g., first color pipeline, second color pipeline), each capable of operating independently. This segmentation allows the system to maintain high operating frequencies in each pipeline while providing flexibility to activate only the necessary pipelines for different memory protocols and topologies, thus resolving the contradiction between speed and adaptability.
Solution Approach 2:
The memory interface circuitry is designed to be dynamically configurable, allowing the number of active color pipelines to be adjusted based on the specific memory protocol and topology being used. This dynamic adaptation enables the system to optimize performance for each configuration while maintaining broad compatibility across different memory standards.
2Adaptability or versatility
If soft/programmable memory interface solutions are used, then flexibility and adaptability are improved, but scheduling efficiency and performance deteriorate
Solution Approach 1:
By segmenting the memory interface into dedicated color pipelines with specialized arbitration logic (RAS arbiter, CAS arbiter, color arbiter), the design achieves both programmability and scheduling efficiency. Each pipeline can be independently configured for different protocols while maintaining optimized memory access scheduling through dedicated arbitration mechanisms.
Solution Approach 2:
Different portions of the memory interface have specialized functions tailored to their specific roles. The color pipelines are optimized for high-speed operation, the arbiters are optimized for scheduling efficiency, and the rate matching circuit is optimized for clock domain crossing. This local optimization allows the overall system to achieve both flexibility and high performance.
3Stability of the object's composition
If in-order memory controllers are used, then determinism in memory scheduling is improved, but memory bandwidth utilization deteriorates
Solution Approach 1:
The memory controller is divided into multiple color pipelines that can process memory access requests in parallel. This segmentation enables out-of-order processing across pipelines while maintaining deterministic behavior within each pipeline through dedicated arbitration logic, thus achieving both high bandwidth utilization and scheduling determinism.
Solution Approach 2:
The system merges in-order processing guarantees within each color pipeline with out-of-order processing capabilities across multiple pipelines. The color arbiter coordinates between pipelines to ensure deterministic overall scheduling while allowing individual pipelines to optimize for bandwidth utilization through parallel out-of-order execution.
Data Source
AI summary
Integrated circuits that include memory interface and controller circuitry for communicating with external memory are provided. The memory interface and controller circuitry may include a user logic interface, a memory controller, and a physical layer input-output interface. The user logic interface may be operated in a first clock domain. The memory controller may be operated in a second clock domain. The physical layer interface may be operated in a third clock domain that is an integer multiple of the second clock domain. The user logic interface may include only user-dependent blocks. The physical layer interface may include memory protocol agnostic blocks and/or memory protocol specific blocks. The memory controller may include both memory protocol agnostic blocks and memory protocol dependent blocks. The memory controller may include one or more color pipelines for scheduling memory requests in a parallel arbitration scheme.