Semiconductor Memory Column Decoder Capacity Balancing
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Solution Overview
Problem
Existing semiconductor memory devices face challenges in maintaining capacity balance between sense and reference sense lines without increasing the number of circuits, leading to inefficiencies in noise tolerance and area usage due to the need for additional column pre-decoder circuits.
Innovation Solution
A column decoder circuit that activates conductor lines for memory cells, connecting them to sense and reference sense lines through switch circuits, allowing for simultaneous selection and capacity balancing without expanding the column pre-decoder circuit, thereby maintaining capacity balance between sense and reference sense lines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a dummy capacity is used to adjust the capacity of the reference sense line, then capacity balance can be achieved, but the adjustment becomes inaccurate and the area increases
Solution Approach 1:
The patent introduces a capacitor as an intermediary element to provide adjustable capacity compensation. The capacitor can be connected to either the sense line or reference sense line through switch circuits, allowing precise capacity adjustment without occupying additional chip area. This intermediary component enables accurate capacity balancing while maintaining compact layout.
Solution Approach 2:
The patent implements variable capacity adjustment by changing the connection state of the capacitor through control signals. The capacity of the reference sense line can be dynamically adjusted by switching the capacitor in or out, enabling precise matching of capacities between sense and reference lines without fixed dummy structures.
2Measurement precision
If separate column pre-decoder circuits are added for each column tree, then capacity balance between sense and reference sense lines can be achieved, but the device complexity and area increase
Solution Approach 1:
The patent merges the capacity balancing function into the existing column pre-decoder circuit by sharing control logic and switch circuits between the first and second column trees. Instead of adding separate pre-decoder circuits, the same control signals and switching mechanisms are utilized to balance capacities, thereby reducing device complexity while achieving the desired capacity balance.
Solution Approach 2:
The column pre-decoder circuit is designed to perform multiple functions: column selection and capacity balancing. The switch circuits controlled by the pre-decoder serve dual purposes of selecting columns and adjusting capacities, eliminating the need for dedicated capacity balancing circuits and reducing overall device complexity.
3Measurement precision
If dummy capacity structures are added to balance capacities, then capacity matching can be achieved, but noise tolerance decreases due to position differences
Solution Approach 1:
The patent achieves equipotentiality in terms of capacity by using a shared capacitor that can be connected to either the sense line or reference sense line. This ensures that both lines have equal capacity values when the capacitor is connected, creating symmetric electrical characteristics that improve noise tolerance by eliminating capacity mismatches that would otherwise create differential noise susceptibility.
Data Source
AI summary
Provided is a semiconductor memory device. The semiconductor memory device includes: a first memory block including a first memory cell; a second memory block including a second memory cell; and a column decoder circuit accessing the first memory cell of the first memory block through a first conductor line and accessing the second memory cell of the second memory block through a second conductor line, wherein the column decoder circuit activates the first and second conductor lines in response to one of an address for reading the first memory cell and an address for reading the second memory cell.