Memory Column Decoder Offset Selection for Edge Error Reduction
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In semiconductor memory devices, the scaling down of memory cells leads to a high probability of data loss or error generation, particularly at the edge areas of sub-arrays, where bit lines with the same relative physical locations are often selected, making it difficult to correct data errors effectively.
Innovation Solution
The implementation of a memory device and system that applies different offset values to sub-arrays and memory chips to select column selection lines, ensuring that bit lines with different relative physical locations are activated, thereby preventing simultaneous activation of bit lines at edge areas and minimizing data errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If memory cells are scaled down to improve integration density, then productivity is improved, but reliability deteriorates due to high probability of data loss or error generation
Solution Approach 1:
The memory device is divided into multiple sub-arrays, and different offset values are applied to each sub-array when selecting column selection lines. This segmentation allows independent error management in different regions, enabling the system to handle errors in scaled-down cells by isolating them within specific sub-arrays while maintaining overall data integrity.
Solution Approach 2:
Different offset values are applied to different sub-arrays based on their specific characteristics and error profiles. This local quality approach allows each sub-array to be optimized for its particular error patterns, improving overall reliability while maintaining high integration density achieved through scaling.
2Ease of operation
If bit lines with the same relative physical locations are selected in sub-arrays, then ease of operation is improved through uniform address mapping, but reliability deteriorates due to simultaneous activation of edge area bit lines causing multi-bit errors
Solution Approach 1:
Different offset values are applied to different sub-arrays, creating an asymmetric address mapping scheme. This asymmetry causes bit lines with the same relative physical location in different sub-arrays to map to different physical bit lines, preventing simultaneous activation of edge area bit lines and eliminating multi-bit errors while maintaining uniform address mapping appearance.
Solution Approach 2:
Instead of mapping bit lines uniformly across all sub-arrays, the invention inverts the approach by applying different offset values that deliberately create non-uniform physical mappings. This inversion prevents the harmful simultaneous activation of edge bit lines while preserving the simplicity of address access from the user perspective.
Data Source
AI summary
A memory device may be provided which includes a memory cell array including a plurality of sub arrays each sub array having a plurality of memory cells connected to bit lines; an address buffer configured to receive a row address and a column address; and a column decoder configured to receive the column address from the address buffer and, for each of the sub arrays, to select a column selection line corresponding to the column address, from among a plurality of column selection lines, based on different offset values applied to the sub arrays, respectively. The selected column selection lines correspond to bit lines having different physical locations, respectively, according to the different offset values.