Memory Column Drowsy Control for Weak Bit Leakage
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Solution Overview
Problem
Existing low-power memory designs, such as power gating, are inefficient when a small portion of a memory array needs to remain active, and static leakage power consumption is significant due to weak bits that cannot maintain their storage state at reduced voltage levels, impairing power-saving techniques and increasing overall power consumption.
Innovation Solution
Implementing fine-grained power reduction by adding a control bit to each subarray of a memory array, allowing for independent power control of each subarray through gating transistors, enabling selective activation or deactivation of memory cells, and using drowsy column control to manage power at a column level to prevent weak bit failure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If array level power gating is applied to place memory into sleep mode, then power consumption is reduced significantly, but the technique becomes inefficient when only a small portion of memory array needs to remain active
Solution Approach 1:
The memory array is divided into multiple independently controllable subarrays, each with its own power gating control. This segmentation allows selective power gating of individual subarrays while keeping others active, resolving the contradiction between achieving power savings and maintaining partial memory activity flexibility.
2Use of energy by moving object
If voltage is reduced to drowsy level to reduce static leakage power consumption, then power savings are achieved, but weak bits cannot maintain their storage state
Solution Approach 1:
Different voltage levels are applied to different columns based on their specific characteristics. Columns containing weak bits maintain full operational voltage to ensure data retention, while columns without weak bits operate at reduced drowsy voltage to minimize leakage power consumption, thus resolving the contradiction between power savings and reliability.
3Use of energy by moving object
If drowsy voltage level is applied to prevent power consumption, then power savings approach sleep mode levels, but weak bits alter their stored value
Solution Approach 1:
The patent implements column-specific voltage control where each column can independently operate at either full voltage or drowsy voltage based on its weak bit status. This ensures that columns with weak bits maintain full voltage to prevent data alteration, while other columns operate at drowsy voltage for maximum power savings, thereby preventing information loss while minimizing power consumption.
4Use of energy by moving object
If fine-grained power control is implemented at column level, then power management efficiency is improved, but device complexity increases
Solution Approach 1:
The memory array is segmented into multiple columns, each with independent power control capability. This segmentation enables fine-grained power management at the column level, allowing selective application of drowsy or full voltage to each column based on its specific power and reliability requirements, thus improving power management efficiency while managing complexity through modular organization.
Data Source
AI summary
In accordance with at least one embodiment, column level power control granularity is provided to control a low power state of a memory using a drowsy column control bit to control the low power state at an individual column level to protect the memory from weak bit failure. In accordance with at least one embodiment, a method of using a dedicated row of bit cells in a memory array is provided wherein each bit in the row controls the low power state of a respective column in the array. A special control signal is used to access the word line, and the word line is outside of the regular word line address space. A mechanism is provided to designate the weak bit column and set the control bit corresponding to that particular column to disable the drowsy/low power state for that column.