Multi-Port Memory Column Redundancy With Fail-Column Switching
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Solution Overview
Problem
Current semiconductor memory devices face challenges in minimizing chip area when a large number of column selection lines are enabled, especially in multi-port memory devices, as existing column redundancy schemes are inefficient and cannot be applied to devices without column addresses.
Innovation Solution
A semiconductor memory device with a column redundancy structure that includes normal and redundant bus connection means, transfer latch sets, and switching mechanisms to selectively connect outputs based on physical position information of fail columns, allowing for efficient data transmission and minimizing chip area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a large number of column selection lines are enabled in multi-port memory devices, then data transmission capability is improved, but chip area increases due to inefficient column redundancy schemes
Solution Approach 1:
The column selection lines are divided into multiple groups, with each group associated with a specific port. This segmentation allows independent control and repair of column lines for each port, reducing the need for comprehensive column redundancy across all ports and thereby minimizing chip area while maintaining data transmission capability.
Solution Approach 2:
The column redundancy structure is designed to serve multiple ports simultaneously. The same redundancy resources can be shared across different ports, allowing the system to maintain high data transmission capability for multiple ports without proportionally increasing chip area, as the redundancy structure performs multiple functions for different port operations.
2Adaptability or versatility
If existing column redundancy schemes are applied to multi-port memory devices without column addresses, then device adaptability is improved, but redundancy efficiency deteriorates
Solution Approach 1:
The system performs preliminary detection of fail columns during manufacturing or initialization and stores the physical position information in a fuse set before normal operation. This preliminary action allows the redundancy mechanism to be pre-configured, enabling efficient column repair during operation without requiring complex real-time detection, thus maintaining high redundancy efficiency while adapting to devices without column addresses.
Solution Approach 2:
A switching mechanism acts as an intermediary between the normal bus connection and redundant bus connection. This switching mechanism selectively connects to either normal or redundant column lines based on pre-stored failure information, enabling efficient column repair without requiring the memory device to have column address capability, thus improving device adaptability while maintaining redundancy efficiency.
Data Source
AI summary
There is provided a column repair technology of a semiconductor memory device. The semiconductor memory device includes: a normal bus connection part for transmitting/receiving data between global data buses and local data buses of each bank; a redundant bus connection part for transmitting/receiving data between global data buses and local data buses of each bank; a fuse set having a physical position information of a fail column; and a switching part for selectively connecting outputs of the normal bus connection part and the redundant bus connection part to the global data buses, which corresponds to the fail column, in response to the physical position information of the fail column. The column redundancy scheme can be applied to semiconductor memory devices having such a structure that a lot of column selection lines are enabled with respect to one column address and can also be applied to a case when a fail column address is not present. Therefore, the redundancy efficiency can be improved and an increase of the chip area can be prevented.