Semiconductor Memory Column Layout to Prevent Conductive Layer Voids
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Solution Overview
Problem
Existing semiconductor memory devices face challenges in preventing insulation defects due to voids formed in the conductive layer during manufacturing, which can lead to defects in the gate insulating film and blockage of gas paths, affecting the integrity of the memory device.
Innovation Solution
The semiconductor memory device is designed with specific alignment patterns of semiconductor column rows in the Y direction, where the pitch of some rows is √3/2 times the adjacent distance, while others are less than this value, which helps in reducing the volume of voids and preventing path blockage during the formation of the conductive layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If the pitch of semiconductor column rows is uniformly set to a standard value, then the manufacturing process is simple, but voids form in the conductive layer causing insulation defects
Solution Approach 1:
The patent applies asymmetry by intentionally creating non-uniform pitch configurations in the semiconductor column rows. Specifically, the pitch in the Y direction is set to different values for different row groups: a first pitch for first semiconductor column rows and a second pitch (different from the first) for second semiconductor column rows. This asymmetric pitch design prevents the formation of voids in the conductive layer that would otherwise occur with uniform pitch, thereby eliminating insulation defects while maintaining manufacturing feasibility.
Solution Approach 2:
The patent implements local quality by applying different pitch values to different regions of the semiconductor column rows. The memory block is divided into regions with first semiconductor column rows having a first pitch and second semiconductor column rows having a second pitch. This localized variation in pitch allows the conductive layer to be properly formed without voids in critical areas, improving film thickness uniformity and preventing insulation defects where they matter most.
2Quantity of substance
If the pitch is reduced to increase device density, then more memory cells fit in the same area, but gas paths become blocked during manufacturing
Solution Approach 1:
The patent resolves the gas path blockage issue by introducing dimensional variation in the pitch configuration. Instead of uniformly reducing pitch in one direction, the patent varies the pitch in the Y direction across different row groups. This dimensional approach allows gas to access formation paths from multiple directions, preventing complete blockage even when pitch is reduced to increase device density. The different pitch values create staggered patterns that maintain manufacturing accessibility.
3Device complexity
If uniform pitch is used for all semiconductor column rows, then the structure is simple, but voids form causing insulation defects in the conductive layer
Solution Approach 1:
The patent applies asymmetry by intentionally creating non-uniform pitch configurations in the semiconductor column rows. Specifically, the pitch in the Y direction is set to different values for different row groups: a first pitch for first semiconductor column rows and a second pitch (different from the first) for second semiconductor column rows. This asymmetric pitch design prevents the formation of voids in the conductive layer that would otherwise occur with uniform pitch, thereby eliminating insulation defects while maintaining manufacturing feasibility.
4Manufacturing precision
If the pitch variation is implemented, then void formation is reduced, but the manufacturing process becomes more complex
Solution Approach 1:
The patent implements local quality by applying different pitch values to different regions of the semiconductor column rows. The memory block is divided into regions with first semiconductor column rows having a first pitch and second semiconductor column rows having a second pitch. This localized variation in pitch allows the conductive layer to be properly formed without voids in critical areas, improving film thickness uniformity and preventing insulation defects where they matter most.
Data Source
AI summary
A semiconductor memory device comprises: a first conductive and second conductive layers extending in a first direction; and first and second semiconductor column rows aligned in a second direction. The first semiconductor column rows each comprise first semiconductor columns aligned in the first direction and facing the first conductive layer. The second semiconductor column rows each comprise second semiconductor columns aligned in the first direction and facing the second conductive layer. For example, a distance in the first direction between center positions of two of the first semiconductor columns adjacent in the first direction is assumed to be a first adjacent distance. In this case, a pitch in the second direction of the first semiconductor column rows is √3/2 or more times the first adjacent distance. Moreover, a pitch in the second direction of the second semiconductor column rows is less than √3/2 times the first adjacent distance.