Semiconductor Memory Column Masking Circuit for Defective Cell Handling
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Solution Overview
Problem
Semiconductor memory devices face issues where defective memory cells can lead to program operations being sensed as incomplete during status check operations, such as program verify operations, due to threshold voltage issues in NAND flash memory devices.
Innovation Solution
The implementation of a semiconductor memory device with a column masking circuit that outputs data change signals to differentiate unused columns from others, allowing data latched in page buffers of defective or redundant memory cells to be changed into operation pass data, thereby preventing program failures during status checks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If data is input as '1' to invalid columns during program operation, then the memory cell should be sensed as being in erase status, but defective memory cells with threshold voltage higher than 0V are sensed as '0' causing program operation to be sensed as incomplete
Solution Approach 1:
The patent extracts and isolates the problematic invalid columns from the normal data processing flow by using column masking circuits to identify and separate defective memory cells. This allows the defective cells to be handled differently (by forcing pass data) without affecting the status check of valid columns, thus resolving the contradiction between maintaining reliability and eliminating defective cell interference.
Solution Approach 2:
The patent performs preliminary identification of invalid columns before the status check operation through column masking circuits that store column data indicating which columns are defective. This preliminary action allows the system to pre-prepare pass data for invalid columns, ensuring they won't interfere with the status check of valid columns, thereby resolving the timing issue where defective cells cause premature fail detection.
2Productivity
If data latched in page buffers is changed simultaneously for invalid columns, then operating speed is enhanced, but additional circuit complexity is introduced to differentiate and control selected columns
Solution Approach 1:
The patent merges the column identification function and the data masking function into a unified column masking circuit structure. The same circuit that identifies invalid columns also controls the data change operation for those columns, reducing the need for separate control mechanisms and minimizing overall circuit complexity while enabling simultaneous data changes for multiple invalid columns.
Solution Approach 2:
The column masking circuit serves multiple functions: it stores column data identifying invalid columns, generates control signals for the data change operation, and coordinates with the page buffer to perform simultaneous data changes. This multi-functionality reduces the need for additional dedicated circuits, balancing the enhancement of operating speed with acceptable circuit complexity.
Data Source
AI summary
A semiconductor memory device includes memory blocks that each include memory cells coupled to bit lines, a column masking circuit configured to output data change signals in response to an address signal indicating bit lines of selected columns among a plurality of columns, and an operation circuit configured to store data of the memory cells transferred through the bit lines and simultaneously change data transferred through the bit lines of the selected columns into operation pass data in response to the data change signals.