Memory Array Column Plane Layout for Single-Pass Metadata Access
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Solution Overview
Problem
Existing memory devices face limitations in retrieving a maximum number of bits per access pass, particularly when storing error correction information and metadata, which can impact performance due to the need for two-pass architectures that increase latency and power consumption.
Innovation Solution
A semiconductor memory device architecture that allows for single-pass access of data, metadata, and error correction parity bits by distributing storage across data and extra column planes, enabling one-pass retrieval of extended additional information without increasing latency or power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of information
If two-pass architecture is used to retrieve data and metadata, then complete information can be accessed, but latency and power consumption increase
Solution Approach 1:
The patent merges the retrieval of data and metadata into a single access pass by utilizing extra column planes that are activated alongside data column planes. The column decoder simultaneously decodes column addresses for both data and metadata storage locations, enabling parallel retrieval of both information types in one operation, thus eliminating the latency penalty of two-pass architectures.
Solution Approach 2:
The patent introduces an additional dimension to the memory architecture by adding extra column planes beyond the traditional data column planes. This dimensional expansion allows metadata to be stored in a separate spatial domain (extra column planes) that can be accessed simultaneously with data column planes, enabling single-pass retrieval without interfering with data access performance.
2Loss of information
If two-pass architecture is used to retrieve data and metadata, then complete information can be accessed, but power consumption increases
Solution Approach 1:
The patent combines metadata retrieval with data retrieval in a single access operation. By activating extra column planes simultaneously with data column planes using the same column decode logic, the system retrieves both data and metadata in one pass, avoiding the additional power consumption that would result from a second access pass.
Solution Approach 2:
The extra column planes serve multiple functions: they store metadata, utilize existing column decode logic, and can be accessed simultaneously with data column planes. This multi-functionality allows the same hardware resources to serve dual purposes without requiring separate dedicated infrastructure, thereby reducing overall power consumption.
3Quantity of substance
If metadata is stored in the memory array with associated data, then information density increases, but access complexity increases
Solution Approach 1:
The patent segments metadata storage into separate extra column planes, distinct from data column planes. This segmentation allows the memory system to handle data and metadata independently through separate storage regions while using unified access logic, thereby increasing information density without proportionally increasing access complexity.
Solution Approach 2:
By storing metadata in an additional dimensional space (extra column planes), the patent increases the total information capacity of the memory array. The existing column decode infrastructure naturally extends to this new dimension, allowing the system to access increased information density without requiring fundamentally more complex access mechanisms.
Data Source
AI summary
Apparatuses, systems, and methods for enhanced metadata information. The memory array includes a number of column planes and an extra column plane. A memory device is set in an x4 single-pass operational mode. In this mode, the memory may store a data codeword in a selected ones of the column planes, and metadata may be stored in a non-selected ones of the column planes and in the extra column plane. An error correction code circuit (ECC) may store parity bits associated with the data and metadata in the non-selected ones of the column planes. In this manner, the data, metadata, and parity may be accessed as part of a single access of the memory array.