Memory Column Repair Using ECC-Corrected Defect Latch Data
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Solution Overview
Problem
As memory device capacity increases, the number of defective memory cells also rises, leading to errors in the repair process due to the limitations of conventional repair methods that rely on non-volatile memory circuits and defective latch circuits, which are prone to errors during boot-up and operational phases.
Innovation Solution
Incorporating error correction code generation and latch circuits to generate and store error correction codes for defective column information, allowing for the correction of errors in defective column data and enabling accurate column repair operations in memory banks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory device capacity is increased, then storage capability is improved, but the number of defective memory cells increases leading to repair errors
Solution Approach 1:
An error correction code (ECC) generation circuit and ECC latch circuit are introduced as intermediary components between the defective column information storage and the repair operation. The ECC generation circuit creates redundancy codes from the defective column information, and the ECC latch circuit stores these codes for later verification during repair operations, thereby mediating the reliability issue caused by increased memory capacity.
Solution Approach 2:
Error correction codes are generated and stored in advance during the boot-up operation before actual memory repair operations are needed. This preliminary action ensures that when repair operations are performed on high-capacity memory devices, the pre-prepared ECC data is available to correct any potential errors in defective column information, preventing repair failures.
2Ease of repair
If conventional repair methods using non-volatile memory circuits are used, then repair functionality is provided, but errors occur during boot-up and operational phases
Solution Approach 1:
The patent implements a feedback mechanism where error correction codes are generated from the defective column information stored in the ECC latch circuit. During operational phases, these ECC codes are used to verify and correct the defective column information, creating a feedback loop that continuously ensures data accuracy and prevents error propagation in repair operations.
3Measurement precision
If error correction code generation and latch circuits are added, then repair accuracy is improved, but device complexity increases
Solution Approach 1:
The error correction functionality is segmented into distinct modular components: an ECC generation circuit that creates correction codes, an ECC latch circuit that stores the codes, and an ECC verification mechanism that applies corrections. This segmentation allows each component to perform its specific function independently, making the overall complex system more manageable and maintainable while achieving high repair accuracy.
Data Source
AI summary
A memory device includes: a non-volatile memory circuit suitable for storing defective column information; a defective latch circuit suitable for receiving and storing the defective column information from the non-volatile memory circuit during a boot-up operation; an error correction code generation circuit suitable for generating an error correction code for correcting an error of the defective column information based on the defective column information; an error correction code latch circuit suitable for storing the error correction code; an error correction circuit suitable for correcting an error of the defective column information transferred from the defective latch circuit based on the error correction code which is transferred from the error correction code latch circuit so as to produce an error-corrected defective column information; and a memory bank suitable for performing a column repair operation based on the error-corrected defective column information.