Memory Column Redundancy Repair with Reduced Latency
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Solution Overview
Problem
Conventional memory circuits with redundant logic introduce additional delays in the memory critical path during repair operations, which can be unacceptable in certain instances, despite the benefits of redundancy in addressing increasing manufacturing defects.
Innovation Solution
A mechanism for reduced latency memory column redundancy repair is implemented by utilizing both outputs of a sense amplifier and selecting one based on repair information, allowing for balanced output loading without significant area penalty, and using data inversion circuits to manage polarity during shifts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional redundant logic is used to repair memory cells, then reliability is improved, but critical path timing increases
Solution Approach 1:
The patent implements dynamic switching between normal operation mode and repair mode. During normal operation, the sense amplifier outputs are used in a conventional single-ended configuration. When a repair is needed, the system dynamically reconfigures to use both differential outputs, selecting the appropriate output based on repair information. This dynamic adaptation allows the system to maintain fast timing during normal operation while enabling repair functionality when needed.
Solution Approach 2:
The patent changes the operational parameters of the sense amplifier from single-ended to differential mode during repairs. By utilizing both outputs of the sense amplifier and selecting based on repair information, the system transforms the timing characteristics of the critical path. The output selection logic dynamically adjusts which signal path is active, effectively changing the timing parameters to reduce latency during repair operations.
2Loss of time
If both sense amplifier outputs are used during repair, then critical path timing is reduced, but device complexity increases
Solution Approach 1:
The sense amplifier, which is already present in the memory array, is made multi-functional. During normal operation, it functions in the conventional single-ended mode. During repair operations, the same sense amplifier is reconfigured to provide differential outputs that can be selectively used. This eliminates the need for separate repair circuitry and reduces overall device complexity while still achieving reduced latency.
Solution Approach 2:
The existing sense amplifier circuitry serves itself by being reconfigured to handle both normal operation and repair functions. The output selection logic uses the repair information to automatically select the appropriate output, making the system self-adapting without requiring external intervention or complex additional control circuits.
3Stability of the object's composition
If dummy devices are connected to unused sense amplifier output, then balanced loading is maintained, but area increases
Solution Approach 1:
Instead of permanently connecting dummy devices to maintain balanced loading, the patent implements a dynamic approach where the same sense amplifier outputs are selectively used based on operational mode. During normal operation, one output is used as before. During repair, both outputs are utilized. This dynamic reconfiguration eliminates the need for permanent dummy devices while still maintaining balanced loading conditions through the output selection logic.
Data Source
AI summary
A memory column redundancy mechanism includes a memory having a number of data output ports each configured to output one data bit of a data element. The memory also includes a number of memory columns each connected to a corresponding respective data port. Each memory column includes a plurality of bit cells that are coupled to a corresponding sense amplifier that may differentially output a respective data bit from the plurality of bit cells on an output signal and a complemented output signal. The memory further includes an output selection unit that may select as the output data bit for a given data output port, one of the output signal of the sense amplifier associated with the given data output port or the complemented output signal of the sense amplifier associated with an adjacent data output port dependent upon a respective shift signal for each memory column.