Semiconductor Memory Column Repair via Master-Slave Block Mapping
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Solution Overview
Problem
Current semiconductor memory devices face increased error possibilities during manufacturing and operation due to reduced chip sizes, and existing repair methods lack flexibility in addressing these errors effectively.
Innovation Solution
A semiconductor memory device architecture that includes a memory cell array with row and column decoders, utilizing fuse information to identify master and slave blocks, allowing for flexible column repair operations by activating specific word-lines and accessing memory cells based on address signals and fuse information.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If semiconductor chips are reduced in size through fine processes, then productivity and integration density are improved, but the possibility of errors during manufacturing and operation increases
Solution Approach 1:
The memory device is divided into multiple row blocks (first row block, second row block) and column blocks, with each block containing multiple segments. This segmentation allows selective activation and repair of specific blocks or segments without affecting the entire memory array, enabling targeted error correction while maintaining high integration density.
Solution Approach 2:
The invention changes the operational parameters by introducing master-slave block configuration where slave blocks are activated based on row address matching. This parameter change enables flexible error handling by switching between normal operation mode and repair mode, allowing the system to maintain reliability despite increased error probability from miniaturization.
2Ease of manufacture
If traditional repair methods are used, then manufacturing complexity is reduced, but the flexibility and effectiveness of error correction is limited
Solution Approach 1:
The repair system is made dynamic through the master-slave block configuration where slave blocks can be selectively activated based on detected errors. The system can adaptively switch between different repair strategies (activating different slave blocks for different error locations) without requiring complex manufacturing processes, achieving both ease of manufacture and repair flexibility.
Solution Approach 2:
The memory device performs self-diagnosis and self-repair through the built-in master-slave block mechanism. When errors are detected in a master block, the system automatically activates corresponding slave blocks to provide replacement functionality, enabling autonomous error correction without external intervention or complex repair manufacturing.
3Adaptability or versatility
If master-slave block configuration with fuse information is implemented, then column repair flexibility is improved, but device complexity increases
Solution Approach 1:
The master-slave block relationships and segment mappings are predetermined and stored in fuse information before operation. This preliminary configuration allows the decoders to quickly determine repair actions without complex real-time calculations, achieving high repair flexibility while keeping the operational decoder logic relatively simple.
Solution Approach 2:
The fuse information acts as an intermediary that stores the complex mapping relationships between master and slave blocks. This intermediary layer separates the complexity of block mapping from the operational decoder logic, allowing the decoders to focus on simple address decoding while the fuse information provides the complex repair routing information.
Data Source
AI summary
A semiconductor memory device comprises a memory cell array including segments disposed at corresponding intersections of row and column blocks, each row block including dynamic memory cells coupled to word-lines and bit-lines, a row decoder that activates a first word-line of a first row block in response to a row address, determines whether the first row block is a master block based on a first fuse information and a second row block is mapped as a slave to the master block, activates a second word-line of the second row block, and outputs a row block information signal, and a column decoder accessing a portion of first memory cells coupled to the first word-line or a portion of second memory cells coupled to the second word-line based on a column address, the row block information signal and a second fuse information.