Pre-Decoded Column Redundancy Circuit for Lower-Area Memory Repair

Solution Overview

Problem

Existing column redundancy circuits in semiconductor memory devices require a large area and significant setup time to replace defective columns with redundancy columns.

Innovation Solution

A column redundancy circuit that includes a pre-decoder unit for performing decoding operations on fault column addresses, a main decoder unit for generating shift signals based on the decoding results, and a shift logic unit for executing column shift operations, thereby reducing the area and setup time required for column redundancy.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a traditional column redundancy circuit is used to replace defective columns, then the memory device can handle faults, but the circuit occupies a large area and requires significant setup time

Engineering Contradiction:

Improvefault handling capabilityVSAvoidcircuit area

Core Design Contradiction:

ReliabilityVSArea of stationary object

Solution Approach 1:

The column address is divided into upper and lower parts, with separate pre-decoders processing each part independently. This segmentation allows parallel processing of address bits, reducing the overall circuit area while maintaining fault handling capability through distributed decoding structures.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

Pre-decoder units perform preliminary decoding of upper and lower column address parts before the main decoding stage. This preliminary action prepares the address signals in advance, reducing the setup time required for the main decoder and enabling faster redundancy operations.

Inventive Principle:

Principle #10Preliminary action

2Reliability

If a traditional column redundancy circuit is used to replace defective columns, then the memory device can handle faults, but the circuit requires significant setup time

Engineering Contradiction:

Improvefault handling capabilityVSAvoidsetup time

Core Design Contradiction:

ReliabilityVSLoss of time

Solution Approach 1:

Pre-decoder units perform preliminary decoding of upper and lower column address parts before the main decoding stage. This preliminary action prepares the address signals in advance, reducing the setup time required for the main decoder and enabling faster redundancy operations.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The circuit uses dynamic shift logic that can adjust the shift amount based on the decoded column address. This dynamic adaptation allows the circuit to optimize its operation for different fault positions, reducing the maximum setup time required across all possible fault scenarios.

Inventive Principle:

Principle #15Dynamics

3Reliability

If more decoding resources are added to handle column faults, then the fault handling capability improves, but the device complexity increases

Engineering Contradiction:

Improvefault handling capabilityVSAvoiddecoder complexity

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The column address is divided into upper and lower parts, with separate pre-decoders processing each part independently. This segmentation allows parallel processing of address bits, reducing the overall circuit area while maintaining fault handling capability through distributed decoding structures.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The pre-decoder outputs for upper and lower column address parts are merged in the main decoder stage, which combines the partially decoded signals to generate the final column select signals. This merging approach maintains comprehensive fault coverage while avoiding the complexity of a fully parallel decoding structure.

Inventive Principle:

Principle #5Merging (Combining)

Data Source

PatentEP4560638A1Column redundancy circuit and memory device including same

Publication Date: 2025.05.28 SAMSUNG ELECTRONICS CO LTD

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AI summary

An example column redundancy circuit of a memory device comprises a pre-decoder circuit, a main decoder circuit, and a shift logic circuit. The pre-decoder circuit is configured to receive a lower column address from a plurality of fault column addresses and perform a first decoding operation, and to receive an upper column address from the plurality of fault column address and perform a second decoding operation. The main decoder circuit includes a plurality of main decoders, and each main decoder is configured to receive a lower signal and one or more upper signals from the pre-decoder circuit and to perform a main decoding operation. The shift logic circuit includes a plurality of shift logics, and each shift logic is configured to generate a shift signal that performs a column shift operation according to a result of the main decoding operation.