Semiconductor Memory Column Repair Using Bit-Line Switches
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Semiconductor chips, particularly dynamic random access memories (DRAMs), face increased error possibilities due to reduced sizes during manufacturing, and initial defect detection is crucial to prevent operational errors, but existing methods lack flexibility in column repair operations.
Innovation Solution
A semiconductor memory device with a memory cell array, bit-line switches, block switches, and a column decoder that controls connections between local I/O lines to repair defective cells using spare bit-lines within or adjacent memory blocks, enhancing column repair flexibility and yield.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If semiconductor chips are reduced in size through fine processes, then manufacturing density increases, but the possibility of errors during manufacturing increases
Solution Approach 1:
The patent applies preliminary action by performing defect detection and repair operations before the semiconductor chip is fully operational. The column repair circuit identifies defective bit-lines during manufacturing testing and pre-configures replacement connections using spare bit-lines, ensuring that defects are addressed before the product reaches the customer, thereby maintaining high reliability despite reduced manufacturing density
Solution Approach 2:
The patent implements beforehand cushioning by incorporating spare bit-lines as a buffer against manufacturing defects. These redundant bit-lines are prepared in advance and can be activated to replace defective bit-lines through the column repair circuit, providing a safety margin that compensates for the increased error probability associated with finer manufacturing processes
2Reliability
If traditional column repair methods are used, then defect detection is performed, but flexibility in column repair operations is limited
Solution Approach 1:
The patent applies universality by designing a column repair circuit that can handle multiple repair scenarios through a unified architecture. The circuit can repair defective bit-lines within the same memory block using intra-block spare bit-lines, or repair bit-lines by accessing spare bit-lines from adjacent memory blocks through block switches, providing versatile repair capability that adapts to different defect locations and types
Solution Approach 2:
The patent uses intermediary elements (block switches and local I/O lines) to connect different memory blocks and enable flexible bit-line replacement. These intermediaries allow the column repair circuit to route signals between adjacent memory blocks, enabling a bit-line in one block to be replaced by a spare bit-line in a neighboring block, thereby significantly increasing repair flexibility
Data Source
AI summary
A semiconductor memory device includes a memory cell array, a bit-line switch, a block switch, and a column decoder. The memory cell array includes memory blocks coupled to at least one word-line and each of the memory blocks includes memory cells. The bit-line switch is connected between a first half local input/output (I/O) line of a first memory block and a second half local I/O line of the first memory block. The block switch is connected between the second half local I/O line of the first memory block and a first half local I/O line of a second memory block adjacent to the first memory block. The column decoder includes a repair circuit that controls connections by applying a first switching control signal to the bit-line switch and a second switching control signal to the block switch.