Memory Device Column Row Switches Power Reduction
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Solution Overview
Problem
Memory devices with high power consumption due to idle bit lines being coupled during read/write operations, leading to increased energy usage.
Innovation Solution
Incorporation of column and row word lines to selectively control switches and bit lines, allowing only necessary bit lines to transmit data during operations, thereby reducing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If all bit lines are coupled to selected memory cells during read/write operations, then data transmission is ensured, but power consumption increases due to idle bit lines
Solution Approach 1:
The patent divides the bit line system into multiple segments using column switches (e.g., SW0-SW7 in memory block 0, SW64-SW71 in memory block 1). Each switch independently controls a specific column of memory cells, allowing only the necessary bit line segments to be activated during read/write operations. This segmentation enables precise control over which bit lines consume power, directly resolving the contradiction between ensuring data transmission reliability and reducing power consumption from idle bit lines.
2Use of energy by moving object
If column and row word lines are added to selectively control switches, then power consumption is reduced, but device complexity increases
Solution Approach 1:
The patent introduces column word lines (e.g., CWL0-CWL7) as a new dimension of control alongside the existing row word lines (WL0-WL255). This creates a two-dimensional addressing scheme where row word lines select specific rows and column word lines select specific columns via the column switches. This dimensional addition enables fine-grained power control without requiring complex modification of existing control logic, as the column word lines operate independently to gate current at the column level.
Data Source
AI summary
A memory device includes a plurality of word lines elongated along a first direction, and at least one memory unit. The at least one memory unit includes a plurality of memory cells, at least one bit line, and at least one column word line. The plurality of memory cells are arranged along a second direction different from the first direction. The at least one bit line is elongated along the second direction, and configured to transmit data of a selected memory cell. The at least one column word line is elongated along the second direction, and configured to control electrical connections between the memory cells and the at least one bit line, wherein the selected memory cell is selected by a corresponding word line and the at least one column word line.