Memory Column Select Swapping for Redundancy Address Collisions
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Solution Overview
Problem
Semiconductor memory devices face issues with defective memory cells that require repair, particularly when multiple column planes share the same column select signal value, leading to address collisions in global column redundancy operations.
Innovation Solution
Implement dynamic column select swapping by programming fuse arrays to swap logical addresses in memory devices, altering column select signals to resolve address collisions, and reroute defective addresses to redundant column planes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If multiple column planes share the same column select signal value, then device complexity is reduced, but address collisions occur in global column redundancy operations
Solution Approach 1:
The patent segments the column select signal into two parts: a plane-specific portion and a shared portion. Each column plane receives a unique plane-specific signal segment that distinguishes it from other planes, while still allowing them to share common column select values within each plane. This segmentation resolves address collisions by ensuring that the combination of plane-specific and shared segments creates unique addresses across all planes.
Solution Approach 2:
The patent applies local quality by making each column plane have a distinct local characteristic through its unique column select signal value or subset. While the overall system allows sharing of column select structures, each plane locally differentiates itself with a unique identifier, ensuring that addresses remain unique globally while maintaining structural efficiency.
2Reliability
If column select signals are made unique across all planes, then address collisions are prevented, but device complexity increases
Solution Approach 1:
The patent merges the column select signal structure by combining plane-specific identifiers with shared column select portions. Instead of creating entirely separate signal paths for each plane, the system merges them into a unified address structure where the same column select logic can be applied within each plane, reducing overall device complexity while maintaining address uniqueness through the plane-specific portion.
Solution Approach 2:
The patent implements universality by designing the column select signal structure to serve multiple functions: it uniquely identifies column planes through plane-specific portions while simultaneously enabling shared column select operations within each plane. This multi-functional design prevents address collisions without requiring entirely separate signal paths for each plane, thereby reducing device complexity.
Data Source
AI summary
Embodiments of the disclosure are drawn to apparatuses and methods for dynamic column select swapping. A memory may have a number of sets of bit lines organized into column planes. If a set of bit lines associated with a first address in a first column plane is defective, it may be repaired by reassigning the first address to a redundant set of bit lines in a global column redundant (GCR) column plane. If a set of bit lines associated with the first address in a second column plane is also defective, then swap logic of the memory may swap the first address to a second address and assign it to the set of bitlines in the second column plane. The second address may then also be repaired by being reassigned to the GCR column plane.