Semiconductor Memory Column Wiring for Stable Select Gate Voltage
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Solution Overview
Problem
The existing semiconductor memory devices face challenges in maintaining optimal resistance values in conductive layers during write operations, leading to potential voltage fluctuations and increased threshold voltages in memory cells, which can result in data integrity issues.
Innovation Solution
The semiconductor memory device configuration includes strategically placed contacts between conductive layers and auxiliary wiring, connected in parallel to reduce resistance values and stabilize voltage, ensuring efficient charge supply to select gate lines during write operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional conductive layer configuration is used, then device structure is simple, but resistance value is high causing voltage fluctuations during write operations
Solution Approach 1:
The conductive layer is divided into multiple segments (first conductive layer and second conductive layer) arranged in different directions. The first conductive layer extends in the first direction intersecting the substrate surface, while the second conductive layer extends in the second direction. This segmentation reduces the overall resistance by providing multiple parallel conduction paths, thereby stabilizing voltage during write operations and improving data integrity.
Solution Approach 2:
The patent transitions from a single-direction conductive path to a multi-dimensional conductive network. By arranging conductive layers in both the first direction (intersecting substrate surface) and the second direction (parallel to substrate surface), the invention creates a two-dimensional conductive architecture that reduces resistance through multiple spatial pathways, preventing voltage fluctuations during write operations.
2Reliability
If conductive layers are arranged in multiple directions, then resistance is reduced and voltage is stabilized, but device structure becomes more complex
Solution Approach 1:
The conductive layers serve multiple functions simultaneously: the first conductive layer provides primary electrical connection in the first direction, while the second conductive layer provides both electrical connection in the second direction and acts as a reference electrode. This multi-functionality reduces the need for additional separate components, maintaining voltage stability without proportionally increasing device complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively reduces resistance in the drain side select gate lines, minimizing voltage fluctuations and maintaining accurate threshold voltages, thus enhancing data storage reliability.
Implementation Method 1
a first electric charge accumulating film disposed between the plurality of first conductive layers and the first semiconductor column
Implementation Method 2
strategically placed contacts between conductive layers and auxiliary wiring, connected in parallel to reduce resistance values
Data Source
AI summary
A semiconductor memory device includes a substrate, a plurality of first conductive layers, a second conductive layer disposed at a position farther from or a position closer to the substrate than the plurality of first conductive layers, a first semiconductor column, a first electric charge accumulating film, a first wiring disposed at a position farther from or a position closer to the substrate than the plurality of first conductive layers and the second conductive layer, a first contact that is disposed between one end of the second conductive layer and the first semiconductor column and is electrically connected to the second conductive layer and the first wiring, and a second contact that is disposed between another end of the second conductive layer and the first semiconductor column and is electrically connected to the second conductive layer and the first wiring.